Physical Design Engineer

Overview :

TekWissen Group isa workforce management provider throughout the USA and many othercountries in the world. This Client is an American multinationalsemiconductor company based in Santa Clara California that developscomputer processors and related technologies for business andconsumer markets.

global company that specializes in manufacturingsemiconductor devices used in computer processing. The company alsoproduces flash memories graphics processors motherboard chip setsand a variety of components used in consumer electronics goods.

JobTitle : Physical Design Engineer

Work Location : Markham ON L3T 7X6

Duration : 15 Months

Work Type : Contract

Job Type : Onsite

Job Description : THE ROLE :

THE ROLE :

Physical Designs Power Optimization iscritical hot topic in IC Physical design.

In this position you will work with globalphysical design team for client AI accelerator / GPU / APU chipsphysical design power optimization / reduction.

Focus on physical designmethodologies implementation to improve chip power consumption fromSynthesize to place & route.

The individual is expected to be an expert indigital physical design it is a plus to have strong ability inFrontEnd or RTL coding experience or Synthesis.

The individual is expected toknow backend physical design very well.

THEPERSON :

Strong selfmotivation for technical topicsquick and deep learner strong communication skill within globalengineering team strong team spirit help and support team members.

KEY RESPONSIBILITIES :

Implementstateofart physical design power optimization methodologies intoSOC project

Maintainand enhance the power optimization methodologies in physical designflow

Closelycollaborate with SOC project design team help / support / drive them toadopt the physical design power optimization methodology

PREFERRED EXPERIENCE :

Preferred5 years or more years of experience in physical design in digitalASIC chips

StrongPnR STA IR / EM PV knowledge / experience

Be familiar with physical design poweroptimization methodologies (eg. Clockgating powergating activityaware PnR power friendly floorplan DVFS multibit rebankingdebanking scan path power etc.)

Expertise in BackEnd (physical design) EDA toolsespecially the power calculation / optimization tools PTPX

Strong flow developand custom script develop ability

Successfully gone through several completeproduct development cycles

Works well with crossfunctional teams

Good communication skills stronginterpersonal skills and the flexibility

ACADEMICCREDENTIALS :

Preferred MSEE with 3 years orBachelor with 5 years of industrial experience in ASIC design

TekWissen Group is an equal opportunityemployer supporting workforce diversity.