Physical Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.

Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges.

We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance THE ROLE : In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets.

The DXIO FEINT / Implementation team is responsible for Synthesis, place & Route, Timing closure / CDC / LINT / DFx for very high speed (>

2G) design with complex I / O clocking. THE PERSON : As a Senior Member of Technical Staff Engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team.

You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule.

This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES : We are currently looking for a senior member who will drive all implementation aspects of next generation IPs.

This team deals with multiple I / O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer. This team is a group of highly experienced ASIC design engineers working on High speed (>

2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure.

The team will work on cutting edge IP for these I / O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide.

PREFERRED EXPERIENCE : Strong experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >

2GHz designs. CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python Academic Credentials : M.S.

in Electrical or Computer Engineering (or equivalent) LOCATION : Markham, ON or Vancouver, BC #LI-TB2 #LI-HYBRID Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE : In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets.

The DXIO FEINT / Implementation team is responsible for Synthesis, place & Route, Timing closure / CDC / LINT / DFx for very high speed (>

2G) design with complex I / O clocking. THE PERSON : As a Senior Member of Technical Staff Engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team.

You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule.

This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES : We are currently looking for a senior member who will drive all implementation aspects of next generation IPs.

This team deals with multiple I / O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer. This team is a group of highly experienced ASIC design engineers working on High speed (>

2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure.

The team will work on cutting edge IP for these I / O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide.

PREFERRED EXPERIENCE : Strong experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >

2GHz designs. CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python Academic Credentials : M.S.

in Electrical or Computer Engineering (or equivalent) LOCATION : Markham, ON or Vancouver, BC #LI-TB2 #LI-HYBRIDBenefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.