Network architect Jobs in Vancouver, BC

About the Role

The Software and Digital Platform Group is looking for a Senior Principal Embedded System Architect & Team Lead to drive our System Architecture team in the HW/SW Co-Design group. This is a critical hybrid role combining high-impact technical leadership, hands-on SoC and IP architectural design, and direct team management. Serving as the primary technical and operational liaison between the architecture team and the Senior Director of HW/SW Co-Design, you will lead the day-to-day execution, technical alignment, and growth of our system and IP architecture team while bringing a critical software-first perspective to hardware co-design.

This is not a role about drawing abstract boxes on slides. It is about actively shaping silicon definition through pre-silicon virtual platforms, data-backed architectural exploration, hands-on data flow analysis, and engineering team leadership. You will manage and mentor a team of strong architects and embedded software experts, while actively contributing to engineering execution. The team’s primary mandate is ensuring a strong software voice is present during the earliest stages of SoC and IP design, well before silicon exists.

Working hand-in-hand with hardware architecture counterparts, you and your team will act as proxies for customers and downstream software teams. You will ensure every major design decision -- from IP block selection to data flow topology -- accounts for software developer experience, real-world performance, field debuggability, and customer usability. We believe that excessive software complexity to compensate for hardware design decisions is a design failure; this role exists to lead the team that prevents exactly that.

Key Responsibilities

Team Leadership & Organizational Liaison

• Architecture Team Management: Direct, mentor, and manage the HW/SW co-design architecture team, driving overall team performance.Directorate Interface: Serve as the primary technical and operational interface between the architecture team and the Senior Director of HW/SW Co-Design, translating group strategy into actionable architectural roadmaps, milestone tracking, and regular progress reviews.Cross-Functional Alignment: Coordinate with digital design, analog, software, validation, and product management engineering leads to resolve design trade-offs and eliminate execution bottlenecks.

Architectural Strategy & Hands-On Engineering

• HW/SW Co-Design & Tradeoff Analysis: Lead SoC co-architecture alongside digital/analog teams to balance hardware complexity, software efficiency, and customer usability at product definition.System & IP Evaluation: Translate customer use cases into quantitative system requirements, assessing data paths and co-defining hardware accelerators to optimize software execution.Core Firmware Strategy: Define and contribute to the core architecture for bootloaders, initialization sequences, microcode, and kernel drivers across target processing nodes.Debug & Usability Advocacy: Champion best-in-class hardware debuggability and observability (CoreSight, JTAG, trace) from early silicon bring-up through field deployment.Customer Proxy: Act as the premier technical authority and voice for customer software teams, ensuring platform APIs and programming models remain intuitive and efficient.

Minimum Qualifications

• Education & Experience: BS/MS in Electrical Engineering, Computer Engineering, or Computer Science with 15+ years of system software architecture, firmware development, and HW/SW co-design experience.Engineering Management: 3+ years of experience in direct engineering management or formal team leadership. (The team in question is very senior, generally self-organizing, and easy to manage day to day.)Embedded Software Expertise: Expert proficiency in C/C++ writing low-level embedded software, bootloaders, and device drivers within RTOS (e.g., Zephyr) and Embedded Linux environments.Computer Architecture: Demonstrable knowledge of memory hierarchies, bus interconnect protocols (AMBA AXI/AHB/APB), DMA engines, and RISC-V/ARM architecture fundamentals.Bring-up & Hardware Debug: Hands-on experience with post-silicon bring-up, JTAG debugging, and reading/evaluating RTL (Verilog/SystemVerilog) to verify hardware intent.

Preferred Qualifications

• Experience scaling and structuring system architecture efforts within semiconductor or IP companies.Hands-on experience using SystemC (TLM 2.0) or transaction-level modeling for early architectural exploration and profiling.Familiarity with pre-silicon simulation platforms like Renode, Virtualizer, etc.Hands-on experience with hardware emulation platforms (e.g., Palladium, Zebu), FPGA prototyping, and continuous integration (CI/CD, Docker) for pre-silicon software workflows.Specialized knowledge in mixed-signal architectures, signal processing accelerators, dynamic power management, and DVFS strategies.Experience defining system-wide debug/trace infrastructure, logic analyzers, and performance modeling tools.Familiarity with hardware security architectures (TrustZone, secure boot, cryptography accelerators).

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