Design Verification Engineer (1-Year Contract)

What You Do at AMD Changes Everything

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Role

The CIT team is a dynamic and innovative team dedicated to pushing the boundaries of hardware development. We are seeking skilled and motivated verification engineers to join our growing team and to contribute to the success of cutting‑edge IPs. We are currently looking for an experienced ASIC Design Verification engineer, who will be involved in all aspects of design verification activities, using the latest methodologies with the help of automation, keeping power and performance in mind. The candidate will utilize/develop a variety of verification components, using the latest verification methodologies to achieve an excellent RTL/Firmware design quality. The CIT team designs AMD chiplet technology. The Design Verification group within this team is responsible for developing a scalable DV flow with new emphasis on automation, power, and performance. The NBIO organization has great diversity of talent across the globe. Our management fosters and encourages continuous technical innovation to showcase successes and facilitate continuous career development.

The Person

• Will demonstrate strong analytical thinking and problem‑solving skills with excellent attention to detail.
• Will have effective communication and writing skills.
• Will have good teamwork and interpersonal skills.

Responsibilities

• Developing testbenches and verification components such as UVCs, models, BFMs, and reusable verification environments.
• Writing, modifying, and maintaining constraint‑random and directed test cases and libraries in System Verilog/UVM.
• Analyzing functional, code, and test plan coverage.
• Implementing assertions, checkers, and monitors.
• Triaging and debugging regressions.
• Deploying industry‑leading verification methodologies such as UVM and Formal Verification.
• Reproducing functional bugs found in silicon, in simulation and/or Formal Verification tools.
• Conducting and participating in code reviews.

Preferred Experience & Skill Sets

• Notable hardware verification experience.
• Must be proficient in Verilog, System Verilog, UVM, and working in Linux and Windows environments.
• Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools.
• Must have excellent programming skills.
• Must have exposure to Makefile and other scripting languages like Perl, Python and Ruby.

Education

Electrical Engineering or Computer Engineering.

Location

Ottawa, Markham, and Vancouver.

Benefits

Benefits offered are described: AMD benefits at a glance.

Equal Opportunity Employer

AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Other Information

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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