Senior Research Scientist Engineer - FEC Design Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people‑first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well‑being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute

Ciena is a leading supplier of optical line and transmission equipment. Join a diverse science and engineering team that invents, designs, and verifies Ciena’s next coherent transceivers. Reporting to Senior Director, Optical Engineering and as a member of the WaveLogic science team you will contribute by means of your ideation, design, modelling and coding skills in communication theory, statistics, digital signal processing, forward error correction, optical physics and/or optical transmission & performance measurements. We provide a learning environment that enables rapid progression to contributing membership in the team.

• Create and analyze forward error correction (FEC) designs for next‑generation high‑speed optical communication systems.
• Work closely with the Modem Signal Processing Team on the implementation of digital algorithms in Ciena products.
• Analyze challenging problems in your areas of knowledge which would be a subset of: coding theory, statistics, signal processing, communications theory, control theory, high‑speed algorithms, and optical physics.
• Create innovative solutions that can be implemented in CMOS.
• Model in MATLAB, Python or C++.
• Interface and collaborate with DSP, hardware, firmware, electro‑optic, systems, and measurements teams.
• Provide feedback & suggestions on existing designs; contribute ideas to improve design procedures.
• Share expertise and best practices with adjacent teams.
• Key DSP technology to enable state‑of‑the‑art coherent optical modem and DWDM systems.
• Verified models and supporting measurements that predict modem performance and define modem specifications, respectively.

The Must Haves

• Education: Ph.D. / Master’s degree in Electrical Engineering or Computer Science with a background in Coding theory/Statistics/Mathematics and/or Digital Communications.
• Experience: 4+ years experience designing and implementing modern FEC such as LDPC, algebraic (RS, BCH, RM) and Polar codes.
• C, C++ experience.

Pay Range

Pay Range: The annual pay range for the position is $102,000 – $163,600.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non‑Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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