Logic Design Engineer

Architect develop and implement breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive industrial and edge computing markets. The IP itself is challenging and of significant scope as it requires implementing very complicated and challenging algorithms in hardware/silicon. It incorporates latest Ethernet technology such as IEEE Time Sensitive Networking (TSN) that extends Ethernet for safety-critical and real-time applications. Analyze architecture design tradeoffs and develop solutions that best meet the requirements. Provide technical leadership to our engineering IP team and assist in project planning and tracking. Oversee the design and implementation of the IP including guidance in design and code reviews. Work with marketing to define feature requirements.

Logic Design Engineer

Architect develop and implement breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive industrial and edge computing markets. The IP itself is challenging and of significant scope as it requires implementing very complicated and challenging algorithms in hardware/silicon. It incorporates latest Ethernet technology such as IEEE Time Sensitive Networking (TSN) that extends Ethernet for safety-critical and real-time applications. Analyze architecture design tradeoffs and develop solutions that best meet the requirements. Provide technical leadership to our engineering IP team and assist in project planning and tracking. Oversee the design and implementation of the IP including guidance in design and code reviews. Work with marketing to define feature requirements.

Business Line Description

Be an integral member of a highly-experienced team in R&D that is responsible for developing IP (Intellectual Property) used in the design of advanced microcontrollers and microprocessors. The IP for which this team is responsible enables a product portfolio with billion USD in annual revenue. Chances are that the car you drive the intelligent devices that pervade your living space and the factories that produce the goods you use will contain one or more of the chips that you contribute to.

We are part of MCU/MPU Engineering a central design organization within NXP developing products for multiple business lines in Automotive Internet of Things (IoT) Networking and Radio Frequency products with expertise in hardware engineering including architecture IP and full SoC Design.

Job Summary:

• Architect design and implement breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive industrial and edge computing markets.

• Responsible for micro-architecture Verilog RTL implementation logic synthesis and timing closure.

• Perform trade-off analysis on performance/area/complexity.

• Ensure front-end to back-end handoff IP quality checks such as Lint/CDC/Synthesis/STA/LEC and other.

• Provide technical support to our engineering IP team including code reviews and assist in project planning and tracking.

• Working closely with IP design verification engineers on planning and execution to ensure the IP is delivered on time and with highest quality.

• Quality documentation for all phases of the project; e.g. quality detailed IP functional and implementation specifications.

• Proactively drive continuous improvement in design methodology.

Key Challenges:

• The IP itself is challenging and of significant scope as it requires implementing very complicated and challenging algorithms in hardware/silicon. It incorporates latest Ethernet technology such as IEEE Time Sensitive Networking (TSN) that extends Ethernet for safety-critical and real-time applications.

• IP requires a well-thought-out scalable micro-architecture and proper parameterization that enables to grow the area/power linearly as the performance capacity and functionality required need to be increased.

• IP developed in the team needs to be of high quality and implementation ready requiring strong interactions with the SoC integration and implementation teams

Cross functional aspects:

• Interaction with architecture software and marketing for IP definition and roadmap

• Work closely with SoC front-end integration and implementation for IP execution.

• Interaction with the application engineering to resolve customer issues.

Job Qualifications:

• Some experience in RTL design of complex digital IP is desireable but not required

• Knowledge in Verilog RTL design logic synthesis coverage analysis and timing closure

• Understanding of IP development methodology and proficiency in front-end design tools

• Knowledge of state-of-the-art networking technologies including TCP/IP protocols is desirable but not required

• Experience with data products such as routers bridges and switches is desirable.

• Security/cryptography experience would be an asset

• Strong architecture and design skills are desirable but not required

• Should be familiar with hardware and software implementation trade-offs.

• Ability to solve system wide problems.

• Algorithm development experience is desirable but not required

• Must work well in a team environment.

• Strong interpersonal communication and documentation skills.

• Bachelors in Computer Science Engineering or related education required.

• 2 years relevant experience

Job location:
Ottawa Canada

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Required Experience:

IC

Employment Type : Full-Time
Experience: years
Vacancy: 1