Temporary Jobs in Markham, ON

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry­ leading CAD tools and cutting ­edge foundry technology. Examples of layout designed by our team include Phase­ Locked Loop (PLL), Delay ­Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

THE PERSON:

The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells and assembly of these lower level cells into IPs. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Over time, responsibilities will expand to include guiding and coordinating off‑shore contractors performing layout tasks.

KEY RESPONSIBILTIES:

• Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
• Floorplan, route, and assemble lower-level cells into macros
• Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
• Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
• Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

This team is essential to the success of AMD as a cutting­ edge company. You will be working on some of the most exciting projects the industry has to offer. It is a very exciting environment and you will be working with the very best in our technology.

PREFERRED EXPERIENCE:

• 2-3 years of experience in custom layout design is preferred
• Strong understanding of CMOS device/circuit theory and analog/digital layout best practices.
• Proficiency with industry-standard layout tools (e.g., Virtuoso, Calibre)
• Experience with LVS, DRC, EMIR and other physical verification flows
• Exposure to advanced nodes (e.g., 2nm/3nm; experience at 5nm/7nm also valued).
• Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR.
• Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus

ACADEMIC CREDENTIALS:

Electrical/Mechanical Engineering Degree and/or Electronics related Diploma

#LI-CC4

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry­ leading CAD tools and cutting ­edge foundry technology. Examples of layout designed by our team include Phase­ Locked Loop (PLL), Delay ­Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

THE PERSON:

The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells and assembly of these lower level cells into IPs. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Over time, responsibilities will expand to include guiding and coordinating off‑shore contractors performing layout tasks.

KEY RESPONSIBILTIES:

• Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
• Floorplan, route, and assemble lower-level cells into macros
• Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
• Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
• Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

This team is essential to the success of AMD as a cutting­ edge company. You will be working on some of the most exciting projects the industry has to offer. It is a very exciting environment and you will be working with the very best in our technology.

PREFERRED EXPERIENCE:

• 2-3 years of experience in custom layout design is preferred
• Strong understanding of CMOS device/circuit theory and analog/digital layout best practices.
• Proficiency with industry-standard layout tools (e.g., Virtuoso, Calibre)
• Experience with LVS, DRC, EMIR and other physical verification flows
• Exposure to advanced nodes (e.g., 2nm/3nm; experience at 5nm/7nm also valued).
• Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR.
• Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus

ACADEMIC CREDENTIALS:

Electrical/Mechanical Engineering Degree and/or Electronics related Diploma

#LI-CC4

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.