Senior engineer Jobs in Markham, ON

Top 5 Required Skills (These are not preferred skills. If the candidate does not have these required skills, they will be rejected completely)

• Professional ASIC hardware design and/or implementation experience.


• Expertise with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.


• Exceptional understanding of ASIC/VLSI concepts


• Experience in logic synthesis using Synopsys and/or Cadence tools.


• Detail oriented with strong analytical and debugging skills

Technologies: What does this temp must know to perform the required job duties (These are not preferred technologies - If they do not have these technologies they will be rejected completely)

Synthesis

Timing constraints/STA

Power analysis

Preferred Qualifications:

• 5+ years of ASIC hardware design related experience


• Strong communication (written and verbal) and collaboration skills


• Working knowledge of UPF specification


• Experience with synthesis, STA


• Experience with High-speed/Low power ASIC design within a Unix environment


• Experience with clock domain crossing techniques and tools


• Scripting skills (Python, PERL, TCL or C)

Required Education:

Required Years of Experience



Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.

Job Description:



Principal Duties & Responsibilities:

• Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.

• Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.

• Collaborates across teams (e.G., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.

• Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.

• Utilizes tools/applications (e.G., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.

• Writes detailed technical documentation for EDA/IP/ASIC projects.

Level of Responsibility:

• Works independently with minimal supervision.

• Decision-making may affect work beyond immediate work group.

• Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc.

• Has a moderate amount of influence over key organizational decisions (e.G., is consulted by senior leadership to make key decisions).

• Tasks require multiple steps which can be performed in various orders;some planning, problem-solving, and prioritization must occur to complete the tasks effectively.





Comments for Suppliers:

· How many rounds of interviews should be expected?

2

· Work Location: (Pick One)

-100% Onsite

-Hybrid (working from home and in office)

-100% Remote (anywhere in the U.S.)



· Shift: Hour/Days of Work

7.5 hrs/day






What we are doing what has not been done.

Shape the future of low power AI subsystems.

Push the boundaries on features and performance.

Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC;a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues.

As we are pioneer new and/or improved functionality, innovate to minimize power consumption. Make a difference, join a team on the cutting edge and become an integral part of growth and momentum.

We are looking for an ASIC Implementation Engineer to be part of our team to innovate and design complex leading, ultra-low power, solutions for audio and context aware applications. We are open to all levels of applicants, with responsibility being commensurate with experience. We are looking for applicants who thrive when presented with constant opportunities for learning and growth and who want to have a large impact on our team.

As part of our team your responsibilities will be focused on key ASIC implementation tasks such as:

• Synthesis


• Timing Constraints


• Implementing ECOs


• STA


• Power intent validation (CLP)


• Lint


• Power Analysis Tasks


• CDC validation


• Model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures


• Contribute to implementation methodologies/ flows

Specific responsibilities will be a function of project and team needs and may vary over time. In addition to implementation tasks the successful candidate may also be asked to perform ASIC design tasks including some RTL development.

Requirements:

• Professional ASIC hardware design and/or implementation experience.


• Expertise with Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.


• Exceptional understanding of ASIC/VLSI concepts


• Experience in logic synthesis using Synopsis and/or Cadence tools.


• Detail oriented with strong analytical and debugging skills

Preferred Qualifications:

• 5+ years of ASIC hardware design related experience


• Strong communication (written and verbal) and collaboration skills


• Working knowledge of UPF specification


• Experience with synthesis, STA


• Experience with High-speed/Low power ASIC design within a Unix environment


• Experience with clock domain crossing techniques and tools


• Scripting skills (Python, PERL, TCL or C)