At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. As well as participating in or leading next generation PHY IP physical design, methodology and flow development, the candidate will work closely with our RTL design team & Analog Team to ensure successful tapeouts.
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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.
#J-18808-LjbffrPhysical Design Engineer II (PNR/Physical Verification/STA/EMIR) • Toronto, Ontario, CA
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