Sr. Design Verification Engineer

2 days ago Be among the first 25 applicants

This range is provided by Arcadia. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

CA$150,000.00 / yr - CA$200,000.00 / yr

Location : Hybrid – Downtown Toronto (4 days / week in office, near Union Station)

Type : Full-time | Permanent

Compensation : $150K–$200K CAD base + early-stage equity

A well-funded AI + semiconductor startup ($30M+ raised) is hiring a junior / intermediate Design Verification Engineer to help reinvent chip verification through AI-native tooling and intelligent automation.

This is a rare chance to get in early, work alongside senior silicon engineers and ML researchers, and build your career on greenfield verification flows that combine traditional SystemVerilog / UVM with cutting-edge AI-driven design tools.

What You’ll Do

• Write and run SystemVerilog / UVM testbenches to validate RTL blocks.
• Develop directed and constrained-random tests for functional coverage.
• Work with senior DV / RTL engineers to define verification plans and metrics.
• Automate test execution, regressions, and coverage collection with Python / scripting.
• Contribute to experiments in AI-assisted verification workflows.

What We’re Looking For

Jumpstart your career in AI-powered chip verification

Competitive salary + meaningful equity in a well-funded, deeply technical startup

Learn directly from senior silicon + AI engineers pushing the frontier

Hybrid role in Toronto — high-trust, low-ego team, chance to grow fast

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