Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.

Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges.

We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance THE ROLE : The focus of this role is to plan, build, and execute the development of Analog and Digital front ends for High Speed PHY that results in power and performance efficient IP subsystems.

THE PERSON : Will be part of AMD's analog and mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2 / HBM3,.

and chip-to-chip Gbps proprietary PHY IP solutions. Must have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES : Work with circuit architects for the implementation of various PHY-AMS macros, blocks, and components.

Own small to medium size complexity AMS macro designs. Work with IP leads / managers following management priorities, design direction and guidelines, deliver quality macro design meeting specs within schedule Work with layout and physical design activities to meet IP PPA specifications Write macro specifications documents including implementation details, as implemented spec metrics and figures of merits Work with test engineers to put together macro test plans for characterization and validation / volume testing Contribute to the overall IP development, characterization and productization PREFERRED EXPERIENCE : 7-10yrs of circuit design experience in high-speed serial and / or parallel Analog / Mixed signal PHY / IO designs.

Design experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals Strong fundamentals and knowledge of Mixed signal, Clocking, high speed custom digital for High speed IO circuit architecture and design Hands-on design experience in multi-Gbps Serdes parallel High BW memory bus (lpddr, hbm, ) and chip-to-chip PHY IPs is preferred.

Hands-on experience in high speed custom digital circuit design (e.g. Serializer, De-Serializer, counters, dividers) design, analysis, and timing verification (transistor level STA) is required.

Knowledge of transistor level static timing analysis and sign-off is needed. Solid understanding of power, area and performance trade-offs in mixed signal design.

Proficient in AMS design flows, tools and methodologies - hands on experience with Cadence AMS design tools and ev, backend reliability (EM, IR, Aging etc), Transistor level STA (Nanotime), Spice simulators XA, SpectreX, Hspice etc.

Excellent written and verbal communication skills with ability to operate with minor supervision and work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic / fast paced environment.

Productive and able to meet deadlines working closely with architecture and project lead / manager to guarantee quality deliverables that meet project's schedule and technical requirements.

Strong ownership of schedule and commit with a no-surprise mindset. ACADEMIC CREDENTIALS : Bachelors or Masters degree in Computer Engineering / Electrical Engineering LOCATION : Markham, ON #LI-DD3 Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE : The focus of this role is to plan, build, and execute the development of Analog and Digital front ends for High Speed PHY that results in power and performance efficient IP subsystems.

THE PERSON : Will be part of AMD's analog and mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2 / HBM3,.

and chip-to-chip Gbps proprietary PHY IP solutions. Must have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES : Work with circuit architects for the implementation of various PHY-AMS macros, blocks, and components.

Own small to medium size complexity AMS macro designs. Work with IP leads / managers following management priorities, design direction and guidelines, deliver quality macro design meeting specs within schedule Work with layout and physical design activities to meet IP PPA specifications Write macro specifications documents including implementation details, as implemented spec metrics and figures of merits Work with test engineers to put together macro test plans for characterization and validation / volume testing Contribute to the overall IP development, characterization and productization PREFERRED EXPERIENCE : 7-10yrs of circuit design experience in high-speed serial and / or parallel Analog / Mixed signal PHY / IO designs.

Design experience in FinFet advanced CMOS process nodes with a solid understanding of transistor device performance and fundamentals Strong fundamentals and knowledge of Mixed signal, Clocking, high speed custom digital for High speed IO circuit architecture and design Hands-on design experience in multi-Gbps Serdes parallel High BW memory bus (lpddr, hbm, ) and chip-to-chip PHY IPs is preferred.

Hands-on experience in high speed custom digital circuit design (e.g. Serializer, De-Serializer, counters, dividers) design, analysis, and timing verification (transistor level STA) is required.

Knowledge of transistor level static timing analysis and sign-off is needed. Solid understanding of power, area and performance trade-offs in mixed signal design.

Proficient in AMS design flows, tools and methodologies - hands on experience with Cadence AMS design tools and ev, backend reliability (EM, IR, Aging etc), Transistor level STA (Nanotime), Spice simulators XA, SpectreX, Hspice etc.

Excellent written and verbal communication skills with ability to operate with minor supervision and work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic / fast paced environment.

Productive and able to meet deadlines working closely with architecture and project lead / manager to guarantee quality deliverables that meet project's schedule and technical requirements.

Strong ownership of schedule and commit with a no-surprise mindset. ACADEMIC CREDENTIALS : Bachelors or Masters degree in Computer Engineering / Electrical Engineering LOCATION : Markham, ON #LI-DD3Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.