Sr. Manager Physical Design CAD Methodology

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.

Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges.

We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance THE ROLE : AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate a strong technical team.

You will manage a Physical Design CAD / Methodology team to develop and maintain world-class Physical Implementation flows and methodologies.

You will collaborate with our internal experts and EDA vendors to plan and drive continuous methodologies improvements, collecting best practices and integrate them into a software designed flow for consistency, efficiency, and ease-of-use.

You will manage your team to provide tools / flows support to the global IP & SoC design teams and work with EDA vendors to resolve tools issues.

THE PERSON : We’re looking for a strong leader with excellent communication skills, technically strong in all aspects of Physical Design, including Synthesis, PnR, CTS & Custom clocktree implementation, LEC, functional ECO, Static timing analysis, EMIR and chip finishing to lead our Physical Implementation CAD / Methodology team.

A candidate with experience leading the IP / SoC Physical Design team with multiple successful tape-outs in modern process nodes (7nm, 5nm, 3nm) using state-of-the-art EDA tools from Cadence, Synopsys, Siemens, etc.

KEY RESPONSIBILITIES : Lead a high-performance Physical Design CAD / Methodology team to develop and maintain world-class Physical Implementation flows from RTL2GDS, including Synthesis, PnR, CTS / Custom clocktree, LEC and ECO.

Collaborate with chip design teams to implement the flows and methodologies to improve Performance, Power and Area (PPA), and Turn-Around-Time (TAT).

Review and drive technical evaluations of EDA tools and provide recommendation. Manage the team in providing tools / flows support to the global design teams.

Work with EDA vendors to resolve tool issues and bugs. Motivate and nurture talent. KEY QUALIFICATIONS : Strong industrial experience in VLSI design.

Strong technical manager experience managing Physical Design team at IP / SoC level with multiple successful tapeouts in advance technodes (10nm and below).

In-depth knowledge in all aspects of Physical Design, including Synthesis, PnR, CTS & Custom clocktree implementation, LEC, functional ECO, Static timing analysis, EMIR and chip finishing.

Experience with driving EDA vendors to make tool improvements or new functions to meet advanced or unique design requirements.

Working knowledge in high-performance design flows using industry-standard EDA tools like Cadence, Synopsys, Siemens, etc.

Solid background in VLSI and CMOS fundamentals Strong mentoring and coaching skills. PREFERRED ACADEMIC CREDENTIALS : Bachelors or Masters degree in computer engineering / Electrical Engineering.

LOCATION : Markham, ON (open to Vancouver, BC) #LI-SL3 Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE : AMD seeks a passionate, collaborative leader with strong technical skills and the initiative to motivate a strong technical team.

You will manage a Physical Design CAD / Methodology team to develop and maintain world-class Physical Implementation flows and methodologies.

You will collaborate with our internal experts and EDA vendors to plan and drive continuous methodologies improvements, collecting best practices and integrate them into a software designed flow for consistency, efficiency, and ease-of-use.

You will manage your team to provide tools / flows support to the global IP & SoC design teams and work with EDA vendors to resolve tools issues.

THE PERSON : We’re looking for a strong leader with excellent communication skills, technically strong in all aspects of Physical Design, including Synthesis, PnR, CTS & Custom clocktree implementation, LEC, functional ECO, Static timing analysis, EMIR and chip finishing to lead our Physical Implementation CAD / Methodology team.

A candidate with experience leading the IP / SoC Physical Design team with multiple successful tape-outs in modern process nodes (7nm, 5nm, 3nm) using state-of-the-art EDA tools from Cadence, Synopsys, Siemens, etc.

KEY RESPONSIBILITIES : Lead a high-performance Physical Design CAD / Methodology team to develop and maintain world-class Physical Implementation flows from RTL2GDS, including Synthesis, PnR, CTS / Custom clocktree, LEC and ECO.

Collaborate with chip design teams to implement the flows and methodologies to improve Performance, Power and Area (PPA), and Turn-Around-Time (TAT).

Review and drive technical evaluations of EDA tools and provide recommendation. Manage the team in providing tools / flows support to the global design teams.

Work with EDA vendors to resolve tool issues and bugs. Motivate and nurture talent. KEY QUALIFICATIONS : Strong industrial experience in VLSI design.

Strong technical manager experience managing Physical Design team at IP / SoC level with multiple successful tapeouts in advance technodes (10nm and below).

In-depth knowledge in all aspects of Physical Design, including Synthesis, PnR, CTS & Custom clocktree implementation, LEC, functional ECO, Static timing analysis, EMIR and chip finishing.

Experience with driving EDA vendors to make tool improvements or new functions to meet advanced or unique design requirements.

Working knowledge in high-performance design flows using industry-standard EDA tools like Cadence, Synopsys, Siemens, etc.

Solid background in VLSI and CMOS fundamentals Strong mentoring and coaching skills. PREFERRED ACADEMIC CREDENTIALS : Bachelors or Masters degree in computer engineering / Electrical Engineering.

LOCATION : Markham, ON (open to Vancouver, BC) #LI-SL3Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.