Senior Engineer - Design

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Job Description:

Microchip’s Datacenter Solutions (DCS) group is looking for an experienced Design Engineer to join the storage controller team developing the next generation of advanced storage controller devices fueling the big data revolution. In this senior role you will take technical ownership of complex subsystems—driving them from architecture and RTL design through verification, silicon bring-up, and post-silicon support—while acting as a subsystem lead and technical mentor to other engineers. Your responsibilities will include, but are not limited to:

Responsibilities

• Act as subsystem lead: own the architecture, micro-architecture, and RTL implementation of complex digital subsystems (100K to 10M+ gates), coordinating schedule, scope, and technical direction across the team.
• Design, code, and integrate synthesizable RTL in SystemVerilog/Verilog and VHDL, ensuring designs meet functional, timing, area, and power targets.
• Maintain and support existing/legacy RTL and IP, and extend it with new features and enhancements while preserving stability, backward compatibility, and design quality.
• Architect and integrate subsystems using standard on-chip interconnect protocols such as AXI/AMBA, including bus fabric, bridging, and interface compliance.
• Implement robust clock domain crossing (CDC) schemes and low-power design techniques (clock gating, power gating, multi-voltage/UPF flows) to meet power, performance, and reliability goals.
• Develop and review subsystem and device-level verification plans, and drive verification closure using SystemVerilog, UVM, and Formal verification methodologies.
• Implement SAS and SATA protocol logic and ensure compliance with applicable storage protocol standards and specifications.
• Apply strong debug skills to track down and resolve complex design, verification, and integration issues, working closely with design, verification, emulation, validation, and firmware teams to ensure timely resolution.
• Lead and support post-silicon bring-up, characterization, and debug; reproduce and root-cause silicon issues in the lab and drive fixes or workarounds.
• Mentor junior engineers, perform design and code reviews, and contribute to design methodology, reuse, and quality improvements.
• Interface with cross-functional teams (architecture, firmware, validation, product, and customers) to align requirements and deliver robust, production-quality silicon.

Requirements/Qualifications:

• Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Significant professional experience (typically 7+ years) in digital ASIC/SoC design and verification.
• Strong RTL design and verification expertise in SystemVerilog and VHDL, including UVM-based and/or Formal verification methodologies.
• Hands-on experience with AXI/AMBA (and related on-chip interconnect) protocols for subsystem integration.
• Solid experience with clock domain crossing (CDC) design and verification techniques and associated CDC analysis tools.
• Practical experience with low-power design methodologies, including clock/power gating and UPF/CPF-based multi-voltage flows.
• Working knowledge of SAS and SATA storage protocols, with the ability to read and apply storage protocol standards.
• Excellent analytical and debug skills, with a proven ability to proactively root-cause and resolve complex hardware issues.
• Demonstrated experience leading a subsystem or feature area, including planning, technical decision-making, and mentoring.
• Experience with post-silicon bring-up, validation, and lab debug.
• Strong scripting and programming skills (e.g., Python, Perl, Tcl, Make) for automation and flows.
• Experience with Unix/Linux operating systems.
• Proficiency with industry simulation and verification tools (e.g., Cadence, Synopsys, Mentor) and waveform viewers.
• Excellent verbal and written communication skills in English.

Good to Have

• Hands-on experience with hardware emulation and FPGA prototyping.
• Experience with DFT and timing closure.
• Familiarity with additional storage and high-speed interface protocols (e.g., NVMe, PCIe).
• Experience defining and improving design and verification methodology across a team.

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:The annual base salary range for this position is $86,000 - $186,000.*

*Range is dependent on numerous factors including job location, skills and experience.

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