Principal RTL Design Engineer

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Job Description:

The Mixed Signal Development Group is responsible for delivering high performance analog, digital and mixed-signal IP to various divisions within Microchip. Leveraging advanced CMOS processes, the team develops mixed-signal integrated circuits for wireline applications. From DDR to flash controller and PHY subsystems, our work enables seamless connectivity between Microchip products and the external world.

As a member of the Mixed-Signal Development Group, you will be working closely with architects, other digital design engineers, verification engineers, firmware engineers, and cross-functional teams. You will contribute to the RTL design and verification of DDR or flash controller/PHY subsystem blocks, playing a key role throughout the ASIC development lifecycle.

Responsibilities:

• Participate in the full ASIC design cycle, including design, verification, backend implementation, silicon bringup and debugging.

• Design RTL using Verilog/SystemVerilog, integrate IP blocks, and implement supporting logic (e.g., clock/reset, Jtag, DFT, SRAMs, etc)

• Run clock domain crossing (CDC) analysis, lint check and power simulations.

• Work closely with verification teams or involve in some verification, review, optimize, and execute verification plans; debug design and simulation issues

• Work closely with backend team on STA timing closure, help analyze timing critical paths and resolve STA timing issues; Run trial synthesis to estimate logic depth and area early in the design cycle

• Work closely with Product Engineering team on characterization planning and execution as well as DFT related tasks, create test plans, test configuration, and provide debug support

• Develop C-based drivers for DDR/Flash PHY, perform simulation-based validation, and support silicon bring-up in the lab

• Produce high-quality design, verification, and test documentation

Requirements/Qualifications:

• Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering/Science, or related field

• 2–10 years of ASIC development experience (level dependent)

• Strong experience in RTL design and verification using Verilog, SystemVerilog, or VHDL

• Hands-on debugging experience with lab equipment (e.g., oscilloscopes, logic analyzers)

• Experience or Knowledge in C/C++ and scripting/automation (Python, Perl, TCL, Shell)

• Working knowledge of DDR and Flash Controller/PHY/memory considered an asset

• Strong problem-solving skills with the ability to work independently and proactively

• Ability to collaborate effectively in a team-oriented environment

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:The annual base salary range for this position is $86,000-$186,000.*

*Range is dependent on numerous factors including job location, skills and experience.

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