Analog Designer (1 year contract)

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

Job Description

The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry­ leading CAD tools and cutting ­edge foundry technology. Examples of layout designed by our team include Phase­ Locked Loop (PLL), Delay ­Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells, assembly of these lower level cells into macros/pads and assembly of these macros/pads into an I/O ring database. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Prior experience training and leading junior resources preferred.

Key Responsibilities

• Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
• Floorplan, route, and assemble lower-level cells into macros
• Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
• Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
• Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

This team is essential to the success of AMD as a cutting­ edge company. You will be working on some of the most exciting projects the industry has to offer. It is a very challenging environment and you will be working with the very best in our technology.

Preferred Experience:

• Must have detailed knowledge of CMOS circuit theory. Ideal candidate will have experience in the 7nm/5nm space.
• Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
• Knowledge of chip level integration and ESD concepts a plus
• Perl programming, TCL and SKILL programming not required, but would be advantages

Academic Credentials:

Electrical/Computer Engineering Degree and/or Electronics related Diploma

#LI-CC4

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Job Description

The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry­ leading CAD tools and cutting ­edge foundry technology. Examples of layout designed by our team include Phase­ Locked Loop (PLL), Delay ­Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signaling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

The candidate will be able to see through the different stages of a project development – from initial floor planning and routing of low level logic gates through top level integration of numerous blocks and ultimately, project tape out related tasks. Day to day responsibilities include layout of lower level cells, assembly of these lower level cells into macros/pads and assembly of these macros/pads into an I/O ring database. You will be running various verification tools at all levels of the design hierarchy. These include DRC, LVS, EM/IR, ERC and Latch up/ESD. Prior experience training and leading junior resources preferred.

Key Responsibilities

• Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
• Floorplan, route, and assemble lower-level cells into macros
• Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
• Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
• Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

This team is essential to the success of AMD as a cutting­ edge company. You will be working on some of the most exciting projects the industry has to offer. It is a very challenging environment and you will be working with the very best in our technology.

Preferred Experience:

• Must have detailed knowledge of CMOS circuit theory. Ideal candidate will have experience in the 7nm/5nm space.
• Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
• Knowledge of chip level integration and ESD concepts a plus
• Perl programming, TCL and SKILL programming not required, but would be advantages

Academic Credentials:

Electrical/Computer Engineering Degree and/or Electronics related Diploma

#LI-CC4

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.