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Design Engineer I
Design Engineer IMicrochip Technology Inc. • Burnaby, Metro Vancouver Regional District, CA
Design Engineer I

Design Engineer I

Microchip Technology Inc. • Burnaby, Metro Vancouver Regional District, CA
12 days ago
Job type
  • Full-time
Job description

Join to apply for the Design Engineer I role at Microchip Technology Inc.

People work at Microchip because we design the technology that powers the world. Our culture supports employee growth, stability, and innovation through a collaborative, diverse environment.

Job Description

Microchip is currently looking for a Design Engineer to join our Communications Business Unit in Burnaby, BC, Canada.

The Communications Business Unit supplies high‑bandwidth optical networking solutions for telecom and hyperscale data center networks. The Product Development team manages the full device R&D cycle from concept to production.

The Role Of The Design Engineer Includes

  • Design digital circuits based on industry standards and market requirements
  • Implement designs in System Verilog RTL code using low‑power design principles
  • Synthesize designs into logic gates with industry‑leading tools and flows
  • Integrate digital and analog circuits with Design‑for‑Test techniques
  • Verify physical timing specifications through Static Timing Analysis (STA)

From time to time, Design Engineers may perform prototype testing in a lab environment to enhance design skills and system‑level insight.

Requirements / Qualifications

  • Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering
  • 1‑2 related Co‑op terms experience (asset)
  • Excellent analytical and debugging skills with a proactive problem‑solving attitude
  • Strong coding skills and experience with System Verilog / Verilog / VHDL, Tcl / Perl / Python, C / C++, XML
  • Experience designing, synthesizing, or verifying RTL on silicon, FPGA, or other platforms
  • Excellent verbal and written communication skills in English
  • Familiarity with communication protocols such as Ethernet, OTN, and others (asset)
  • Experience with Synopsys or Cadence tool flows for synthesis, verification or STA (asset)
  • Experience with 65 nm and smaller silicon process technologies (asset)
  • Travel Time

    0% – 25%

    Pay Range

    Annual base salary : $76,000 – $114,000 (varies by location, skills, and experience). Total compensation includes base pay, restricted stock units, quarterly bonuses, health benefits, retirement plans, and an IESPP program.

    To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees.

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    Design Engineer • Burnaby, Metro Vancouver Regional District, CA

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