Physical Design Engineer (Power Optimization)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.

Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges.

We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance THE ROLE : Physical Design’s Power Optimization is critical hot topic in IC Physical design.

In this position, you will work with global physical design team for AMD AI accelerator / GPU / APU chips physical design power optimization / reduction.

Focus on physical design methodologies implementation to improve chip power consumption, from Synthesize to place & route.

The individual is expected to be an expert in digital physical design, it is a plus to have strong ability in Front-End or RTL coding experience or Synthesis.

The individual is expected to know back-end physical design very well. THE PERSON : Strong self-motivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit help and support team members.

KEY RESPONSIBILITIES : Implement state-of-art physical design power optimization methodologies into SOC project Maintain and enhance the power optimization methodologies in physical design flow Closely collaborate with SOC project design team, help / support / drive them to adopt the physical design power optimization methodology PREFERRED EXPERIENCE : Extensive experience in physical design in digital ASIC chips Strong PnR, STA, IR / EM, PV knowledge / experience Be familiar with physical design power optimization methodologies, (eg.

Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-banking, scan path power, etc.

Expertise in Back-End (physical design) EDA tools, especially the power calculation / optimization tools, PTPX Strong flow develop and custom script develop ability Successfully gone through several complete product development cycles Works well with cross-functional teams Good communication skills, strong interpersonal skills and the flexibility ACADEMIC CREDENTIALS : Master's in Electrical Engineering with extensive industrial experience in ASIC design is preferred LOCATION : Markham, Canada #LI-BM1 #LI-Hybrid Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE : Physical Design’s Power Optimization is critical hot topic in IC Physical design. In this position, you will work with global physical design team for AMD AI accelerator / GPU / APU chips physical design power optimization / reduction.

Focus on physical design methodologies implementation to improve chip power consumption, from Synthesize to place & route.

The individual is expected to be an expert in digital physical design, it is a plus to have strong ability in Front-End or RTL coding experience or Synthesis.

The individual is expected to know back-end physical design very well. THE PERSON : Strong self-motivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit help and support team members.

KEY RESPONSIBILITIES : Implement state-of-art physical design power optimization methodologies into SOC project Maintain and enhance the power optimization methodologies in physical design flow Closely collaborate with SOC project design team, help / support / drive them to adopt the physical design power optimization methodology PREFERRED EXPERIENCE : Extensive experience in physical design in digital ASIC chips Strong PnR, STA, IR / EM, PV knowledge / experience Be familiar with physical design power optimization methodologies, (eg.

Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-banking, scan path power, etc.

Expertise in Back-End (physical design) EDA tools, especially the power calculation / optimization tools, PTPX Strong flow develop and custom script develop ability Successfully gone through several complete product development cycles Works well with cross-functional teams Good communication skills, strong interpersonal skills and the flexibility ACADEMIC CREDENTIALS : Master's in Electrical Engineering with extensive industrial experience in ASIC design is preferred LOCATION : Markham, Canada #LI-BM1 #LI-HybridBenefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.