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Web designer • gatineau qc
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Digital ASICFPGA Designer
TekWissen LLCOttawa, Ontario, CanadaWeb / Communication Officer
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ASIC Designer
SyntronicOttawa, ON, CA- L'Ancienne-Lorette, QC (from $ 48,557 to $ 215,000 year)
- Gatineau, QC (from $ 48,557 to $ 215,000 year)
- L'Assomption, QC (from $ 48,557 to $ 215,000 year)
- Longueuil, QC (from $ 71,158 to $ 152,215 year)
- Thunder Bay, ON (from $ 36,163 to $ 145,650 year)
- Winnipeg, MB (from $ 50,281 to $ 144,718 year)
- Rocky Mountain House, AB (from $ 50,827 to $ 127,606 year)
- Newmarket, ON (from $ 90,812 to $ 123,500 year)
- Dollard-Des Ormeaux, QC (from $ 120,491 to $ 121,514 year)
- Owen Sound, ON (from $ 56,550 to $ 121,139 year)
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Digital ASICFPGA Designer
TekWissen LLCOttawa, Ontario, Canada- Full-time
- Temporary
Overview :
TekWissen is a global workforce management provider headquartered in Ann Arbor Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara California that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories graphics processors motherboard chip sets and a variety of components used in consumer electronics goods.
Position : Digital ASIC / FPGA Designer
Location : Ottawa ON
Duration : 12 Months
Job Type : Temporary Assignment
Work Type : Hybrid
THE ROLE :
Digital ASIC / FPGA Designer with at least 15 years of experience and a bachelors degree in engineering or computer science
Experience in front-end ASIC design EDA flows including : Synopsys Design / Fusion Compiler Synopsys VCS simulation; MBIST DFT; CDC Lint tools
Excellent RTL ASIC / FPGA design skills in Verilog and System Verilog
Knowledge of networking standards and wired communications protocols (such as Ethernet)
Experience with scripting languages such as Python Perl and TCL.
Experience with Client Vivado Design Suite
Top Must Have Skills :
ASIC RTL Design
Verilog / SystemVerilog
Clock Domain Crossing (CDC) Analysis
Functional simulation debug
RTL Synthesis
TekWissen Group is an equal opportunity employer supporting workforce diversity.
Key Skills
Graphic Design,CSS,HTML5,Adobe Creative Suite,Fpga,Digital design,Web Design,Adobe Photoshop,Adobe Illustrator,Responsive Web Design,Sketch,Adobe Indesign
Employment Type : Full Time
Experience : years
Vacancy : 1