Computer programming Jobs in Boisbriand, QC
Lead C++ Software Engineer
Cadence Design Systems, Inc.ROYAL ,MOUNT
Programmeur(se) logiciel en chef(fe) | Lead Software Programmer - Ghostpunch
PTWQC, CA
CNC Programmer (Mastercam)
TechaidVille St-Laurent- Promoted
Vision engineer
St-AmourMonteregie
Software developer, APIs and integrations (senior)_PP
CroesusLaval, Canada
CNC (computer numerical control) machinist
Usinage D.D.R. Inc.Saint-Laurent, QC, CA
Front-end Developer
Dynacom Technologies Inc.Laval, QC- Promoted
Lead Software Developer - Montreal
Snowed In StudiosQC, CA- Promoted
Software Designer / Concepteur(trice) logiciel
EXFOVille Saint-Laurent, Quebec, CA
Controls Technician (DDC)
Annexair Inc.Saint-Germain-de-Grantham, Québec, Canada
Senior Digital ASIC / FPGA Verification Engineer
Ciena Canada, Inc.Bldg C, Terry Fox,Ottawa,Canada
Methods Agent
BombarbierSt-Laurent, Québec, CA, H4R 1K2
Office Administration Part Time Work from Home Computer Job
EA SolutionsLaval, QC, ca
System Software Specialist
Solution SFTSaint-Laurent, QC, CA
Safety Critical Embedded Software Developer
Mannarino Systems & Software Inc.Saint-Laurent, Québec, Canada
Tests Means and Tools Team Lead
CS GROUPQC, ca
Scada Engineer
MTS RecruitingSaint-Laurent, QuebecLead C++ Software Engineer
Cadence Design Systems, Inc.ROYAL ,MOUNT- Full-time
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to develop and enhance the Protium FPGA-Based Prototyping product which is used by leading CPU / GPU / HyperScaler companies for pre-Silicon software validation of their SOC’s.
You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Compiler working with a small team of super star engineers to develop our next generation FPGA based verification platform.
Responsibilities :
Enhance Static Timing Analysis (STA)in the Protium Compiler.
Work includes implementingnew algorithms in C++to support Multi-cycle constraints and other SDC exceptions such as set_false_path.
Optimize memory and runtime by using multi-threading and distributed computing .
Develop the EDA automation flow for the platform with other engineers.
Write Design Specifications and Unit Tests for your code
Position Requirements / Qualifications :
- Bachelors in Computer Science, Electrical / Computer Engineering and a minimum of 4 years of related experience, or Masters and a minimum of 2 years of related experience, or PhD with thesis in a relevant area.
- Ideally you are a solid contributor in the FPGA or ASIC prototyping / synthesis / verification space and have delivered great QoR on these platforms.
- You are well renowned for your excellent programming skills in C / C++ and you document your work clearly and love talking about it to your team.
- You are very comfortable with Verilog or SystemVerilog and understand digital circuits .
- Usage of popular logic simulators and some experience in multi-threaded / concurrent programming are pluses.
- The role requires exceptional software skills and Object Oriented Programming experience to be a good match
- Knowledge and experience of ML / AI algorithms and deployment in production code a plus
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