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Design Verification Engineer
Design Verification EngineerAMD • Vancouver, Metro Vancouver Regional District, CA
Design Verification Engineer

Design Verification Engineer

AMD • Vancouver, Metro Vancouver Regional District, CA
18 days ago
Job type
  • Full-time
Job description

Design Verification Engineer – AMD

Location : Vancouver, BC

Hybrid work environment.

Job Details

Seniority level : Mid-Senior level

Employment type : Full-time

Job function : Engineering, Design, and Information Technology

Industry : Semiconductor Manufacturing

Key Responsibilities

  • Writing / Implementing / Reviewing Test Plans
  • Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re‑usable Verification Environments
  • Writing, Modifying, and Maintaining Random and Directed Test Cases and Libraries in SystemVerilog / UVM
  • Analyzing Functional, Code, and Test Plan Coverage
  • Implementing Assertions, Checkers, and Monitors
  • Utilizing In-House and 3rd Party IP / SOC CAD and EDA Tools for Design Verification
  • Deploying Industry‑Leading Verification Methodologies such as UVM
  • Triaging and Debugging Regressions
  • Reproducing Functional Bugs found in Silicon with Simulation Verification tools
  • Conducting and participating in Code Reviews
  • Technical leadership including driving projects from start to finish and Design verification sign‑off

Preferred Experience

  • Digital Design in RTL, Verilog HDL
  • Testbench Architecture, SystemVerilog, UVM
  • C / C++, Java, or other object‑oriented programming language
  • Perl, Ruby, Shell‑scripting, UNIX / LINUX Environment
  • VCS, NCSIM, Questa, or other simulator and associated waveform viewers such as Verdi
  • PC System Architecture : PCI Express, x86, ARM
  • On-Chip Bus Interfaces and Architectures : AMBA AXI, OCP, PIPE
  • Academic Credentials

  • Master's or Bachelor's degree with working experience in ASIC area
  • The Person

  • Creative innovator and thinker who loves technical problems and detail-oriented tasks
  • Exhibits relentless commitment to help the team meet quality and development goals on schedule
  • Drives to learn and perform at their highest potential in a technical capacity
  • Thrives in both a team environment and in individual contribution
  • Communicates openly and clearly in meetings, presentations, emails, and reports
  • Able to learn independently and acquire new skills required for the job
  • Flexible in working hours to accommodate working with co‑workers in different time zones
  • Benefits and Policies

    Benefits offered are described : AMD benefits at a glance.

    Equal Opportunity

    AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

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    Design Verification Engineer • Vancouver, Metro Vancouver Regional District, CA

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