Senior Physical Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE : Physical Design’s Power Optimization is a critical hot topic in IC Physical Design. In this position, you will work with the global physical design team for AMD AI accelerator / GPU / APU chips' physical design power optimization / reduction. Focus on physical design methodologies implementation to improve chip power consumption, from synthesis to place & route. The individual is expected to be an expert in physical design; it is a plus to have a strong ability in Synthesis. The individual is expected to know back-end physical design very well. THE PERSON : Strong self-motivation for technical topics, quick and deep learner, strong communication skills within the global engineering team, strong team spirit help and support team members. KEY RESPONSIBILITIES : Implement state-of-the-art physical design power optimization methodologies into the SOC project Maintain and enhance the power optimization methodologies in the physical design flow Closely collaborate with the SOC project design team, help / support / drive them to adopt the physical design power optimization methodology PREFERRED EXPERIENCE : Experience in physical design for chip design Strong PnR, STA, IR / EM, PV knowledge / experience Be familiar with physical design power optimization methodologies (eg, Clock-gating, power-gating, activity-aware PnR, power-friendly floorplan, DVFS, multibit re-banking, de-banking, scan path power, etc.) Expertise in Back-End (physical design) EDA tools, especially the power calculation / optimization tools, PTPX Strong flow development and custom script development ability Successfully gone through several complete product development cycles Works well with cross-functional teams Good communication skills, strong interpersonal skills, and flexibility ACADEMIC CREDENTIALS : Bachelors or Masters degree in computer engineering / Electrical Engineering LOCATION : Markham, CA #LI-SC3 #LI-HYBRID Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.THE ROLE : Physical Design’s Power Optimization is a critical hot topic in IC Physical Design. In this position, you will work with the global physical design team for AMD AI accelerator / GPU / APU chips' physical design power optimization / reduction. Focus on physical design methodologies implementation to improve chip power consumption, from synthesis to place & route. The individual is expected to be an expert in physical design; it is a plus to have a strong ability in Synthesis. The individual is expected to know back-end physical design very well. THE PERSON : Strong self-motivation for technical topics, quick and deep learner, strong communication skills within the global engineering team, strong team spirit help and support team members. KEY RESPONSIBILITIES : Implement state-of-the-art physical design power optimization methodologies into the SOC project Maintain and enhance the power optimization methodologies in the physical design flow Closely collaborate with the SOC project design team, help / support / drive them to adopt the physical design power optimization methodology PREFERRED EXPERIENCE : Experience in physical design for chip design Strong PnR, STA, IR / EM, PV knowledge / experience Be familiar with physical design power optimization methodologies (eg, Clock-gating, power-gating, activity-aware PnR, power-friendly floorplan, DVFS, multibit re-banking, de-banking, scan path power, etc.) Expertise in Back-End (physical design) EDA tools, especially the power calculation / optimization tools, PTPX Strong flow development and custom script development ability Successfully gone through several complete product development cycles Works well with cross-functional teams Good communication skills, strong interpersonal skills, and flexibility ACADEMIC CREDENTIALS : Bachelors or Masters degree in computer engineering / Electrical Engineering LOCATION : Markham, CA #LI-SC3 #LI-HYBRID

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.