Digital Design Engineer

About the RoleAs a Digital Design Engineer at The Six, you will be responsible for the design and bring-up of our memory PHY IP. You will be involved in the whole design process, from architecture to GDS realization. You will also be actively engaged with customers to ensure successful integration into their SOC.Responsibilities and DutiesArchitectural design including interface definition, power and frequency state logic, link training algorithm, phase tracking algorithm, PLL and DLL calibration, data path optimization and DFTImplementation of PHY and Testchip RTL logic in VerilogFunctional modeling of PHY custom circuits in VerilogDesign specification for verification team and external customerReview test plan and verification environmentParticipation in testplan developmentTestchip and PHY bring-up flow developmentCustomer integration and bring-up supportRequirementsBachelor / Master in Electrical or Computer EngineeringExtensive RTL design experience in Verilog / VHDLDeep understanding of timing constraints and clock domain crossing (CDC)Knowledge of full ASIC design flow including synthesis, place and route, scan insertion, etcExperience with design or validation of memory interfaces such DDR, LPDDR, HBM and GDDRProficient in scripting languages (Perl, Python, Tcl, etc)TSS is looking to hire an exceptional Digital Design Engineer to join our team in Markham, Ontario.If you love to work and grow in a fast-paced environment where you can innovate and truly enjoy your work, please send your resume to careers@thesixsemi.com and include the name of the position in the subject line.