ASIC Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE : ASIC Design Engineer who will be involved in all aspects of IP RTL design. THE PERSON : Exhibits relentless commitment to help the team meet quality and development goals on schedule Drives to learn and perform at his or her highest potential in a technical capacity Thrives in both a team environment and in individual contribution Communicates openly and clearly in meetings, presentations, emails, and reports Able to learn independently and acquire new skills required for the job Creative and innovator and thinker who loves technical problems and detail-oriented tasks KEY RESPONSIBLITIES : IP RTL design for AMDs PCI Express (PCIe) IP used for all next generation server, clients, GPU and Semi-custom products. Work closely with IP and system architects to micro-architect cutting edge features. Apply low power design techniques to existing logic and maintain overall system performance. Focus on timing, LINT and CDC closure to ensure high quality RTL. Support verification and debug of the ASIC throughout various stages of the project. PREFERRED EXPERIENCE : Strong working experience in RTL coding using Verilog HDL Experience in design with multiple clock domains Experience in using lint and CDC tools Experience in developing specification Understanding of high-speed I / O protocols (PCIe, USB, SATA, Ethernet…) ACADEMIC CREDENTIALS : Bachelors or Masters degree in Computer Engineering / Electrical Engineering LOCATION : Markham, Ontario CA #LI-DD3 #LI-HYBRID Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.THE ROLE : ASIC Design Engineer who will be involved in all aspects of IP RTL design. THE PERSON : Exhibits relentless commitment to help the team meet quality and development goals on schedule Drives to learn and perform at his or her highest potential in a technical capacity Thrives in both a team environment and in individual contribution Communicates openly and clearly in meetings, presentations, emails, and reports Able to learn independently and acquire new skills required for the job Creative and innovator and thinker who loves technical problems and detail-oriented tasks KEY RESPONSIBLITIES : IP RTL design for AMDs PCI Express (PCIe) IP used for all next generation server, clients, GPU and Semi-custom products. Work closely with IP and system architects to micro-architect cutting edge features. Apply low power design techniques to existing logic and maintain overall system performance. Focus on timing, LINT and CDC closure to ensure high quality RTL. Support verification and debug of the ASIC throughout various stages of the project. PREFERRED EXPERIENCE : Strong working experience in RTL coding using Verilog HDL Experience in design with multiple clock domains Experience in using lint and CDC tools Experience in developing specification Understanding of high-speed I / O protocols (PCIe, USB, SATA, Ethernet…) ACADEMIC CREDENTIALS : Bachelors or Masters degree in Computer Engineering / Electrical Engineering LOCATION : Markham, Ontario CA #LI-DD3 #LI-HYBRID

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.