Hardware Development Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE PERSON : Will have strong analytical / problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills THE ROLE : The Memory IO team is looking for a passionate and experienced Design Engineering Lead for RTL and Firmware development of high-speed LPDDR,DDR and inter-chip IO IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs (microarchitecture, design, team leadership) as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge and differentiating IPs. RESPONSIBILITIES : RTL design for memory I / O PHY Digital Architecture development from pathfinding, coding, verification to physical implementation PHY link layer design, implementation & verification with Analog and System architect. Micro-architecture of digital blocks for memory IO, hardware / firmware partitioning. PHY Analog / Digital co-design, DSP algorithm development and implementation for Analog Front End. Digital design and RTL coding Timing Synthesis & Drive Physical implementation RTL design quality and reliability methodology and flow development Direction and supervision of other RTL and firmware designers Definition and optimization of training hardware and algorithms including optimization in silicon Working with internal customers to define functional boundaries and specs PREFERRED EXPERIENCE : Digital design engineering experience with successful tape-outs and technical leadership Excellent knowledge of Verilog, C, C++ and a scripting language; experience with Python, Perl and TCL is a plus Knowledge of clocking architectures, synchronization, and CDC methodology DSP, Control Theory and SSLMS / RMS algorithm experience SERDES, DDR, Memory Controller, or MAC Design experience is preferred Strong understanding of computer organization / architecture. Firmware Development experience is a plus Mixed signal RTL experience is a plus Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.) Laboratory experience, including the use of equipment : oscilloscopes, logic analyzers, etc. EDUCATION : Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus. Location : Markham, ON #LI-SL3 Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.THE PERSON : Will have strong analytical / problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills THE ROLE : The Memory IO team is looking for a passionate and experienced Design Engineering Lead for RTL and Firmware development of high-speed LPDDR,DDR and inter-chip IO IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs (microarchitecture, design, team leadership) as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge and differentiating IPs. RESPONSIBILITIES : RTL design for memory I / O PHY Digital Architecture development from pathfinding, coding, verification to physical implementation PHY link layer design, implementation & verification with Analog and System architect. Micro-architecture of digital blocks for memory IO, hardware / firmware partitioning. PHY Analog / Digital co-design, DSP algorithm development and implementation for Analog Front End. Digital design and RTL coding Timing Synthesis & Drive Physical implementation RTL design quality and reliability methodology and flow development Direction and supervision of other RTL and firmware designers Definition and optimization of training hardware and algorithms including optimization in silicon Working with internal customers to define functional boundaries and specs PREFERRED EXPERIENCE : Digital design engineering experience with successful tape-outs and technical leadership Excellent knowledge of Verilog, C, C++ and a scripting language; experience with Python, Perl and TCL is a plus Knowledge of clocking architectures, synchronization, and CDC methodology DSP, Control Theory and SSLMS / RMS algorithm experience SERDES, DDR, Memory Controller, or MAC Design experience is preferred Strong understanding of computer organization / architecture. Firmware Development experience is a plus Mixed signal RTL experience is a plus Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.) Laboratory experience, including the use of equipment : oscilloscopes, logic analyzers, etc. EDUCATION : Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus. Location : Markham, ON #LI-SL3

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.