6 Principal, SMTS & MTS ML Compiler Engineers needed

Our client is an established team of 30 ML compiler experts who research, develop and ship the AI compiler for billions of deployed mobile, automotive, AR / VR, IOT and laptop ML execution engines.

They seek engineers with strong background in algorithms, compilers and / or graph theory who are proficient with contemporary software development flows and are eager to explore / transition into the area of Machine Learning compilers, infrastructure for high performance inference and training tools, Pytorch graph optimizations and AI acceleration software stacks.

The team do not require previous ML experience and continue to successfully train and develop strong candidates with no ML background to become equally strong ML compiler and system experts.

Your Software development or Algorithmic work experience or Compiler Optimization experience or hands on Deep Learning experience would be a good fit with our best customer where I am dealing directly with a highly responsive hiring VP.

You would be involved in driving the development of their ML software stack, enhance the performance of the ML compiler and contribute to future evolution of their AI SW / HW solutions.

Team has freedom to work on a broad set of problems spanning full stack design, software architecture, algorithm development, kernel optimization, performance modeling and hardware accelerator architecture / design.

The team is now growing into new areas such as Pytorch graph optimizations, on-device training and LLM fine-tuning / personalization while continuing to innovate and deliver new compiler optimization algorithms / code.

For senior members, we are seeking team leads that have a record of mentoring capable junior engineers so that they can fulfill their potential. You would also :

• Invent, critique and analyze alternative technical and schedule options to reach consensus-driven team plans.
• Define and implement efficient compiler algorithms that Map ML workloads to HW
• Analyze ML / AI workload performance and power on HW and determine cost-effective methods of improving these metrics.
• Define, model and tune algorithms for ML kernels and HW features to improve mappings of ML / AI workloads across multiple HW generations.
• Create and drive flow to monitor evolving on-silicon performance to discover, root-cause and remedy discrepancies.

Interested? Please email your resume and we can set up an exploratory zoom call. The HM has hired 3 Sr. Staff Engineers from us and looking to hire 6 more.

Very generous salary, RSU's and Signing Bonuses.