Memory PHY RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE : The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Microarchitectural design and RTL implementation of IP features. Synthesis, STA, CDC / RDC, UPF Design / Simulation, Power optimization, Gate sim. PHY Digital Architecture development from pathfinding, coding, verification to physical implementation Collaborate with Firmware team to develop firmware sequences and algorithms Analyze RTL design for power optimization and timing optimization Collaborate with Design Verification team to execute on design features Timing Synthesis & Drive Physical implementation Participate in design specification and RTL code reviews. PREFERRED EXPERIENCE : Digital design engineering experience Excellent knowledge of Verilog, System Verilog, C and a scripting language; experience with Python, Perl and TCL is a plus Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Knowledge of clocking architectures, synchronization, and CDC methodology SERDES, DDR, Memory Controller, or MAC Design experience is preferred Strong understanding of computer organization / architecture. Mixed signal RTL experience is a plus Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS : Bachelors or Masters degree in Computer Engineering / Electrical Engineering LOCATION : Markham, Vancouver (open to Vancouver, BC and Ottawa, ON sites) #LI-SL3 Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.THE ROLE : The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Microarchitectural design and RTL implementation of IP features. Synthesis, STA, CDC / RDC, UPF Design / Simulation, Power optimization, Gate sim. PHY Digital Architecture development from pathfinding, coding, verification to physical implementation Collaborate with Firmware team to develop firmware sequences and algorithms Analyze RTL design for power optimization and timing optimization Collaborate with Design Verification team to execute on design features Timing Synthesis & Drive Physical implementation Participate in design specification and RTL code reviews. PREFERRED EXPERIENCE : Digital design engineering experience Excellent knowledge of Verilog, System Verilog, C and a scripting language; experience with Python, Perl and TCL is a plus Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Knowledge of clocking architectures, synchronization, and CDC methodology SERDES, DDR, Memory Controller, or MAC Design experience is preferred Strong understanding of computer organization / architecture. Mixed signal RTL experience is a plus Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS : Bachelors or Masters degree in Computer Engineering / Electrical Engineering LOCATION : Markham, Vancouver (open to Vancouver, BC and Ottawa, ON sites) #LI-SL3

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.