Lead SMU Validation Engineer - Data Center GPU

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

THE ROLE:

As an Lead SMU (System Management Unit) Validation Engineer in the Data Center and GPU Accelerated Processing Division, you will drive SMU hardware and power-management validation for AMD Data Center GPU products across pre-silicon, bring-up, post-silicon enablement, and system-level debug. You will own key areas of validation strategy and execution while partnering with architecture, design, firmware, diagnostics, platform, automation, customer engineering, and program teams to deliver high-quality next-generation AI and HPC products.

THE PERSON:

The ideal candidate is a motivated technical leader with strong experience in SoC power-management validation, SMU hardware features, firmware interactions, subsystem communication, and system-level debug.

You can independently drive validation planning, issue triage, root-cause analysis, and closure while influencing cross-functional teams, mentoring engineers, and communicating clearly with technical and program stakeholders.

KEY RESPONSIBILITIES:

• Own SMU hardware validation planning and execution across emulation, ASIC bring-up, post-silicon enablement, regression, and sustaining phases.
• Develop validation plans for SMU sub-blocks and power-management features, including bootcode, clocking, fuse, SMN, SMUIO, thermal, RSMU, security-related interactions, and other system-management functions.
• Lead debug triage, root-cause analysis, and issue closure across hardware, firmware, platform, diagnostics, and system-level interactions.
• Partner with architecture, design, firmware, diagnostics, platform, automation, customer engineering, and program teams to align scope, risks, dependencies, and exit criteria.
• Build and improve automation, validation content, debug-analysis scripts, and regression checks to improve coverage, efficiency, and repeatability.
• Review RTL, specifications, firmware interfaces, register maps, and validation collateral to identify coverage gaps and improve validation effectiveness.
• Support lab-based and system-level debug using platform tools, firmware logs, register-level analysis, and standard measurement equipment.
• Support customer and sustaining issues by providing SMU technical expertise, debug guidance, and issue-resolution support.
• Mentor engineers and help improve team validation methodology, debug practices, and product quality.

PREFERRED EXPERIENCE:

• Strong experience in semiconductor validation, silicon bring-up, SoC validation, firmware validation, or hardware/software integration.
• Hands-on experience with power-management validation, SMU/PMFW functionality, SoC control fabrics, clocking, reset, fuse, thermal, voltage-regulator, or platform-management features.
• Experience developing validation plans, test content, automation, and debug methodologies for complex SoC or GPU products.
• Strong debug skills across hardware, firmware, software, diagnostics, and platform interactions.
• Experience with emulation, simulation, or FPGA/prototyping environments.
• Proficiency in Python and C/C++ for automation, test infrastructure, or debug-analysis tools.
• Familiarity with Linux, lab bring-up, register-level debug, firmware logs, and platform debug tools.
• Ability to execute independently, manage priorities, influence cross-functional teams, and drive technical issues to closure.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field preferred.

LOCATION:

Markham, ON

#LI-SL2

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

As an Lead SMU (System Management Unit) Validation Engineer in the Data Center and GPU Accelerated Processing Division, you will drive SMU hardware and power-management validation for AMD Data Center GPU products across pre-silicon, bring-up, post-silicon enablement, and system-level debug. You will own key areas of validation strategy and execution while partnering with architecture, design, firmware, diagnostics, platform, automation, customer engineering, and program teams to deliver high-quality next-generation AI and HPC products.

THE PERSON:

The ideal candidate is a motivated technical leader with strong experience in SoC power-management validation, SMU hardware features, firmware interactions, subsystem communication, and system-level debug.

You can independently drive validation planning, issue triage, root-cause analysis, and closure while influencing cross-functional teams, mentoring engineers, and communicating clearly with technical and program stakeholders.

KEY RESPONSIBILITIES:

• Own SMU hardware validation planning and execution across emulation, ASIC bring-up, post-silicon enablement, regression, and sustaining phases.
• Develop validation plans for SMU sub-blocks and power-management features, including bootcode, clocking, fuse, SMN, SMUIO, thermal, RSMU, security-related interactions, and other system-management functions.
• Lead debug triage, root-cause analysis, and issue closure across hardware, firmware, platform, diagnostics, and system-level interactions.
• Partner with architecture, design, firmware, diagnostics, platform, automation, customer engineering, and program teams to align scope, risks, dependencies, and exit criteria.
• Build and improve automation, validation content, debug-analysis scripts, and regression checks to improve coverage, efficiency, and repeatability.
• Review RTL, specifications, firmware interfaces, register maps, and validation collateral to identify coverage gaps and improve validation effectiveness.
• Support lab-based and system-level debug using platform tools, firmware logs, register-level analysis, and standard measurement equipment.
• Support customer and sustaining issues by providing SMU technical expertise, debug guidance, and issue-resolution support.
• Mentor engineers and help improve team validation methodology, debug practices, and product quality.

PREFERRED EXPERIENCE:

• Strong experience in semiconductor validation, silicon bring-up, SoC validation, firmware validation, or hardware/software integration.
• Hands-on experience with power-management validation, SMU/PMFW functionality, SoC control fabrics, clocking, reset, fuse, thermal, voltage-regulator, or platform-management features.
• Experience developing validation plans, test content, automation, and debug methodologies for complex SoC or GPU products.
• Strong debug skills across hardware, firmware, software, diagnostics, and platform interactions.
• Experience with emulation, simulation, or FPGA/prototyping environments.
• Proficiency in Python and C/C++ for automation, test infrastructure, or debug-analysis tools.
• Familiarity with Linux, lab bring-up, register-level debug, firmware logs, and platform debug tools.
• Ability to execute independently, manage priorities, influence cross-functional teams, and drive technical issues to closure.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field preferred.

LOCATION:

Markham, ON

#LI-SL2

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.