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Design Verification EngineerAMD • Vancouver, British Columbia, CA
Design Verification Engineer

Design Verification Engineer

AMD • Vancouver, British Columbia, CA
30+ days ago
Job type
  • Full-time
Job description

Overview

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence while being direct, humble, collaborative and inclusive of diverse perspectives.

Role

AMD is looking for motivated individuals seeking opportunities to solve complex problems in a fast‑paced work environment. The successful candidate will be involved in all aspects of AMD's next‑generation products, including verifying PCI Express designs using the latest UVM standard, developing comprehensive test plans to ensure coverage closure and gaining exposure to all stages of ASIC design.

Person

  • Creative innovator and thinker who loves technical problems and detail‑oriented tasks
  • Exhibits relentless commitment to help the team meet quality and development goals on schedule
  • Drives to learn and perform at highest potential in a technical capacity
  • Thrives in both a team environment and individual contribution
  • Communicates openly and clearly in meetings, presentations, emails and reports
  • Able to learn independently and acquire new skills required for the job
  • Flexible in working hours to accommodate co‑workers in different time‑zones

Key Responsibilities

  • Writing, implementing and reviewing test plans
  • Developing testbenches and verification components such as UVCs, models, BFMs and reusable verification environments
  • Writing, modifying and maintaining random and directed test cases and libraries in SystemVerilog/UVM
  • Analyzing functional and code coverage
  • Implementing assertions, checkers and monitors
  • Utilizing in‑house and third‑party IP/SOC CAD and EDA tools for design verification
  • Deploying industry‑leading verification methodologies such as UVM
  • Triaging and debugging regressions
  • Reproducing functional bugs found in silicon in simulation verification tools
  • Conducting and participating in code reviews
  • Providing technical leadership, including driving projects from start to finish and verification sign‑off

Preferred Experience

  • Testbench architecture, SystemVerilog, UVM
  • Digital design in RTL, Verilog HDL
  • Working experience in ASIC
  • C/C++, Java or other object‑oriented programming language
  • Perl, Ruby, Shell‑scripting, UNIX/Linux environment
  • VCS, NCSim, Questa or other simulator and associated waveform viewers such as Verdi
  • PC system architecture: PCI Express, x86, ARM
  • On‑chip bus interfaces and architectures: AMBA AXI, OCP, PIPE

Academic Credentials

  • Masters or bachelor’s degree in electrical or computer engineering

Equal Opportunity Employer

AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Artificial Intelligence

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. The AMD “Responsible AI Policy” is available.

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Design Verification Engineer • Vancouver, British Columbia, CA

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