Senior FPGA Emulation Engineer, ASIC Verification Infrastructure

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

The Multimedia & Graphics Infrastructure and Methodology team is looking for a Senior FPGA Emulation Engineer, ASIC Verification Infrastructure to drive hardware emulation modeling and FPGA-based acceleration solutions in support of AMD ASIC IP teams. We develop and enable scalable, high-performance hardware design infrastructure, verification frameworks, and methodologies spanning modeling, design verification, flow automation, and platform deployment.

As part of this team, you will help shape next-generation design and verification flows by architecting and implementing modeling and verification frameworks, while gaining hands-on exposure to design, debug, automation, and acceleration technologies.

THE PERSON:

In this role, you will contribute to the development and deployment of FPGA-based hardware acceleration solutions, working closely with globally distributed design and verification teams to deliver robust, scalable emulation and verification platforms.

• Proven experience working on complex hardware designs with hands-on involvement in architecting and developing hardware emulation models and design verification infrastructure.
• Demonstrated ability to collaborate effectively with global teams distributed across multiple geographies and time zones.
• Strong communication skills, with a history of effective documentation and independent execution of tasks from concept to completion.

KEY RESPONSIBILITIES:

• Architect and develop FPGA-based hardware acceleration solutions.
• Create and port Verilog RTL designs to FPGA platforms.
• Develop or adapt test libraries, emulation models, and test cases from existing IP.
• Perform subsystem-level and multi-IP verification.
• Automate and improve build and run efficiency.
• Understand existing C/C++ and UVM testbench environments and identify opportunities for improvement.
• Collaborate with global design verification teams and drive effective execution of verification plans.

PREFERRED EXPERIENCE:

• Strong understanding of the hardware design and verification lifecycle.
• Hands-on verification experience with C/C++ and SystemVerilog testbench development.
• Experience with x86, ARM, or other industry-standard microprocessor architectures.
• Experience verifying clocking, reset, power-up sequences, and power management features.
• Familiarity with low-power design and verification techniques is a plus.

ACADEMIC CREDENTIALS:

• Undergrad degree required. Bachelor’s or master’s degree in computer engineering/Electrical Engineering is preferred.

This role is not eligible for Visa sponsorship.

#LI-BM1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

The Multimedia & Graphics Infrastructure and Methodology team is looking for a Senior FPGA Emulation Engineer, ASIC Verification Infrastructure to drive hardware emulation modeling and FPGA-based acceleration solutions in support of AMD ASIC IP teams. We develop and enable scalable, high-performance hardware design infrastructure, verification frameworks, and methodologies spanning modeling, design verification, flow automation, and platform deployment.

As part of this team, you will help shape next-generation design and verification flows by architecting and implementing modeling and verification frameworks, while gaining hands-on exposure to design, debug, automation, and acceleration technologies.

THE PERSON:

In this role, you will contribute to the development and deployment of FPGA-based hardware acceleration solutions, working closely with globally distributed design and verification teams to deliver robust, scalable emulation and verification platforms.

• Proven experience working on complex hardware designs with hands-on involvement in architecting and developing hardware emulation models and design verification infrastructure.
• Demonstrated ability to collaborate effectively with global teams distributed across multiple geographies and time zones.
• Strong communication skills, with a history of effective documentation and independent execution of tasks from concept to completion.

KEY RESPONSIBILITIES:

• Architect and develop FPGA-based hardware acceleration solutions.
• Create and port Verilog RTL designs to FPGA platforms.
• Develop or adapt test libraries, emulation models, and test cases from existing IP.
• Perform subsystem-level and multi-IP verification.
• Automate and improve build and run efficiency.
• Understand existing C/C++ and UVM testbench environments and identify opportunities for improvement.
• Collaborate with global design verification teams and drive effective execution of verification plans.

PREFERRED EXPERIENCE:

• Strong understanding of the hardware design and verification lifecycle.
• Hands-on verification experience with C/C++ and SystemVerilog testbench development.
• Experience with x86, ARM, or other industry-standard microprocessor architectures.
• Experience verifying clocking, reset, power-up sequences, and power management features.
• Familiarity with low-power design and verification techniques is a plus.

ACADEMIC CREDENTIALS:

• Undergrad degree required. Bachelor’s or master’s degree in computer engineering/Electrical Engineering is preferred.

This role is not eligible for Visa sponsorship.

#LI-BM1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.