Performance Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

We are looking for a seasoned Design Verification Engineer who will be part of the performance verification team working on next generation of a complex multi-subsystem IP(NBIO Org) for client, server, embedded, graphics, and semi-custom chips. The role involves working directly on multiple industrial standards like PCIe, CXL, I/O Virtualizations, Memory management as well as x86/ARM SoC architectures. This is a multidisciplinary function/role, working in a close collaboration with IP design and verification managers, system Architects, SOC verification and validation teams on performance aspects of the multi-subsystem IP. We also work closely with performance architects and modelling teams to execute case studies to help HW Architects to drive the design and features definition for the next generation of products.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Collaborate with performance architects, design and verification engineers to understand the new performance features to be verified.
• Create test plan documentation, based on use cases defined by hardware designers and architects, coordinate technical reviews within the team
• Drive regression triage meetings with team, and drive daily scrum for various projects as well as manage backlogs and planning
• Actively involved in developing new ideas to improve the engineering infrastructure, methodology and execution
• Provide technical support to the team to debug both functional and performance test failures to determine the problem’s root cause.
• Work with RTL designers and SoC/IP Architects to resolve HW and configuration related performance issues
• Analyze and review performance results with SoC/Chip leads and suggest potential solutions.
• Work on performance case studies with Performance architects, facilitating research through generating results and scripts to analyze results
• Write detailed reports to publish performance results and present them in various management readouts

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to video codec system or other multimedia solutions.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Vancouver, Markham, Ottawa

#LI-TB2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

We are looking for a seasoned Design Verification Engineer who will be part of the performance verification team working on next generation of a complex multi-subsystem IP(NBIO Org) for client, server, embedded, graphics, and semi-custom chips. The role involves working directly on multiple industrial standards like PCIe, CXL, I/O Virtualizations, Memory management as well as x86/ARM SoC architectures. This is a multidisciplinary function/role, working in a close collaboration with IP design and verification managers, system Architects, SOC verification and validation teams on performance aspects of the multi-subsystem IP. We also work closely with performance architects and modelling teams to execute case studies to help HW Architects to drive the design and features definition for the next generation of products.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Collaborate with performance architects, design and verification engineers to understand the new performance features to be verified.
• Create test plan documentation, based on use cases defined by hardware designers and architects, coordinate technical reviews within the team
• Drive regression triage meetings with team, and drive daily scrum for various projects as well as manage backlogs and planning
• Actively involved in developing new ideas to improve the engineering infrastructure, methodology and execution
• Provide technical support to the team to debug both functional and performance test failures to determine the problem’s root cause.
• Work with RTL designers and SoC/IP Architects to resolve HW and configuration related performance issues
• Analyze and review performance results with SoC/Chip leads and suggest potential solutions.
• Work on performance case studies with Performance architects, facilitating research through generating results and scripts to analyze results
• Write detailed reports to publish performance results and present them in various management readouts

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Desirable assets with prior exposure to video codec system or other multimedia solutions.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Vancouver, Markham, Ottawa

#LI-TB2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.