Physical Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

In this role, you will play a critical part in shaping AMD’s next‑generation graphics processor IP by driving best‑in‑class Performance, Power, and Area (PPA) outcomes. You will partner closely with RTL, Physical Design, Methodology, and CAD teams to translate innovative architectures into high‑quality silicon, influencing design decisions early and throughout the execution cycle. This is a highly visible, hands‑on role where your technical leadership and insight will directly impact product success from concept to tape‑out.

THE PERSON:

You are passionate about modern processor architectures and bring a collaborative, analytical, and detail‑oriented approach to complex design challenges. You communicate clearly across disciplines and time zones, take strong ownership of your work, and are comfortable navigating ambiguity while driving results. You value teamwork, proactively identify risks and opportunities, and enjoy mentoring others while contributing to a culture of technical excellence, continuous learning, and mutual respect.

KEY RESPONSIBILITIES:

• Lead engineer driving PPA improvements for critical graphics blocks, and serves as main point of contact from Physical Design to RTL teams.
• Study block microarchitecture and data flow to determine optimal memory placement & Synthesis/P&R Recipes.
• Work with RTL design to understand upcoming feature changes and resolve potential bottlenecks for frequency, LOL and timing issues early in the project cycle.
• Collaborate with RTL designers to explore additional opportunities for area and power savings.
• Partner with Methodology and CAD teams to optimize tools/flows for achieving best in class PPA.
• Deliver best known recipes to PD tile owners for achieving Performance, Power and Area targets.
• Analyze stdcell library offerings and work with library team to evaluate PPA impact/benefit from different standard cell offerings.

PREFERRED EXPERIENCE:

• Experience in ASIC Physical Design from RTL to GDSII.
• Strong RTL analysis skills including Verilog, Timing Analysis, and library understanding.
• Strong knowledge in design margining methodology, low voltage design, silicon – STA correlation.
• Hands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics.
• Strong communication, time management, and presentation skills.
• Excellent analytical, problem solving, and attention to detail skills.
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion.
• Provide mentorship and guidance to junior and senior engineers, and be an effective team player.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

In this role, you will play a critical part in shaping AMD’s next‑generation graphics processor IP by driving best‑in‑class Performance, Power, and Area (PPA) outcomes. You will partner closely with RTL, Physical Design, Methodology, and CAD teams to translate innovative architectures into high‑quality silicon, influencing design decisions early and throughout the execution cycle. This is a highly visible, hands‑on role where your technical leadership and insight will directly impact product success from concept to tape‑out.

THE PERSON:

You are passionate about modern processor architectures and bring a collaborative, analytical, and detail‑oriented approach to complex design challenges. You communicate clearly across disciplines and time zones, take strong ownership of your work, and are comfortable navigating ambiguity while driving results. You value teamwork, proactively identify risks and opportunities, and enjoy mentoring others while contributing to a culture of technical excellence, continuous learning, and mutual respect.

KEY RESPONSIBILITIES:

• Lead engineer driving PPA improvements for critical graphics blocks, and serves as main point of contact from Physical Design to RTL teams.
• Study block microarchitecture and data flow to determine optimal memory placement & Synthesis/P&R Recipes.
• Work with RTL design to understand upcoming feature changes and resolve potential bottlenecks for frequency, LOL and timing issues early in the project cycle.
• Collaborate with RTL designers to explore additional opportunities for area and power savings.
• Partner with Methodology and CAD teams to optimize tools/flows for achieving best in class PPA.
• Deliver best known recipes to PD tile owners for achieving Performance, Power and Area targets.
• Analyze stdcell library offerings and work with library team to evaluate PPA impact/benefit from different standard cell offerings.

PREFERRED EXPERIENCE:

• Experience in ASIC Physical Design from RTL to GDSII.
• Strong RTL analysis skills including Verilog, Timing Analysis, and library understanding.
• Strong knowledge in design margining methodology, low voltage design, silicon – STA correlation.
• Hands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics.
• Strong communication, time management, and presentation skills.
• Excellent analytical, problem solving, and attention to detail skills.
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion.
• Provide mentorship and guidance to junior and senior engineers, and be an effective team player.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-LC3

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.