Company : Qualcomm Canada ULC
Job Area : Engineering Group >
ASICS Engineering
General Summary
Qualcomm enables a world where everyone and everything can be intelligently connected. As the world's leading wireless tech innovator, we push the boundaries of what's possible to enable next‑gen experiences and drive digital transformation for a smarter, connected future.
We are searching for an ASIC Design and Implementation Engineer to be part of the Compute DSP / AI Processor Design Team responsible for developing hardware to support AI / ML and video processing systems in Qualcomm Snapdragon processors.
This is a New Position.
Principal Duties and Responsibilities
- Develop module, hard‑macro, and floor planning specifications for digital compute processing cores, bus interfaces, and other system‑on‑chip functions
- Investigate, analyze, and present performance, area, power, and system cost tradeoffs for hard macros using constraint, timing, and floorplan driven optimizations
- Contribute to and / or drive floor planning and implementation meetings within a multi‑disciplinary team
- Implement and debug timing constraints, RTL, Power Intent Specification, Design for Test (DFT), and clock functions
- Perform netlist synthesis, Formal Verification, and Static Timing Analysis of hard macros
- Implement ECOs using automated design flows
- Complete design checks and analysis such as lint, CDC, power intent, and static timing reports
- Develop methodology and automation for design / synthesis using TCL / make / python scripts
Minimum Qualifications
Bachelor's degree in Engineering, Science, or related field3+ years ASIC design and netlist implementation experienceLegally permitted to work on‑site in Markham, CanadaPreferred Qualifications
Proven experience implementing high‑speed logic designs with RAM and several clock domainsStrong verbal and written communication skills to concisely evaluate and deliver specifications, plans, and design analysesDetail oriented with strong analytical, critical thinking, and debugging skillsCollaborative and able to adapt to challenging team objectives in a multi‑national organizationUnderstanding of ASIC / VLSI design concepts
Bus interfaces (AHB / AXI)Clock crossingRAM and FIFO integrationASIC clock network analysisStatic timing analysis debug strategyTiming constraints development and debugPower optimizationProven design and implementation skills using several of the following languages and tools
Synthesis : Synopsys FC (or DCG / NXT), Cadence GenusStatic Timing : PrimetimePower Intent and Analysis : UPF, CLP, PTPX, PowerProFormal Verification : Conformal, FormalityDesign / DV : RTL, VCS, Verdi, Questa, Xcelium, SpyglassScripting Languages : TCL, Python, Perl, UNIX shellPay range and Other Compensation & Benefits
$104,900.00 - $154,900.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and the opportunity for annual RSU grants.
Applicants
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application / hiring process, contact disability‑accomodations@qualcomm.com.
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