Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

The Memory and Systems IP (MSIP) team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in. We are currently looking for an experienced Digital Design Verification engineer, who will be involved in different aspects of verification activities. The candidate will manage/utilize a variety of verification components to ensure the robustness of RTL designs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Develop and enhance SystemVerilog/UVM-based testbenches for verifying new features.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in memory sub-system architecture.
• Create staging and test plans for new feature development.
• Effectively testing a design by understanding the functional and performance goals.
• Take ownership of different verification tasks.
• Improve productivity through automation using languages like Perl, Python and Tcl/Tk.

PREFERRED EXPERIENCE:

• Architected and developed complex verification environments in SystemVerilog or C++.
• Have personally implemented verification tests, sequences, scoreboards, checkers, assertions and coverage groups.
• Experience with Low Power Verification and debug methodology is a plus.
• Exposure to RTL design, software development, formal verification, or other related domains.
• Excellent communication, management, and presentation skills.
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE).
• Good attention to detail and creative thinking ability.
• Self-starter and team player with strong analytical skills and independent working ability.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred.

LOCATION: Markham, Ontario, Canada

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#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

The Memory and Systems IP (MSIP) team is seeking a skilled and motivated verification engineer to join our team and to contribute to the success of the projects we are involved in. We are currently looking for an experienced Digital Design Verification engineer, who will be involved in different aspects of verification activities. The candidate will manage/utilize a variety of verification components to ensure the robustness of RTL designs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Develop and enhance SystemVerilog/UVM-based testbenches for verifying new features.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in memory sub-system architecture.
• Create staging and test plans for new feature development.
• Effectively testing a design by understanding the functional and performance goals.
• Take ownership of different verification tasks.
• Improve productivity through automation using languages like Perl, Python and Tcl/Tk.

PREFERRED EXPERIENCE:

• Architected and developed complex verification environments in SystemVerilog or C++.
• Have personally implemented verification tests, sequences, scoreboards, checkers, assertions and coverage groups.
• Experience with Low Power Verification and debug methodology is a plus.
• Exposure to RTL design, software development, formal verification, or other related domains.
• Excellent communication, management, and presentation skills.
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE).
• Good attention to detail and creative thinking ability.
• Self-starter and team player with strong analytical skills and independent working ability.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred.

LOCATION: Markham, Ontario, Canada

#LI-DD3
#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.