Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE : As a Silicon Design Engineer 2, you will develop, enhance, and maintain industry‑leading physical design (PD) flows, methodologies, and foundational library infrastructure. You will work closely with front‑end designers, physical design teams, CAD, and methodology leads to build scalable, automated, and robust solutions spanning all three verticals of the PD organization. Your work will directly impact execution efficiency, QoR, schedule predictability, and silicon quality across multiple programs. THE PERSON : You have a strong passion for physical design, EDA flow development, and innovative methodologies that enable efficient, high‑quality silicon. You are detail‑oriented, highly technical, and enjoy solving complex design challenges with clean, maintainable automation. You are a strong collaborator with excellent communication skills, and you thrive in an environment where you can influence methodologies and define best practices for the organization. KEY RESPONSIBILITIES : Develop, maintain, and support physical design flows across synthesis, APR, STA, power, and DRC / LVS domains. Build scalable methodologies and infrastructure for all three PD verticals (flows, libraries, execution). Own library validation infrastructure including timing, physical, and power model checking and regression. Work with EDA teams to evaluate, integrate, and qualify new tool features and methodologies. Drive automation to improve execution efficiency, debuggability, runtime, and tool QoR. Partner with physical design teams to debug flow issues, develop new features, and improve design convergence. Create regression frameworks and dashboards to ensure flow, methodology, and library quality at scale. Contribute to documentation, onboarding material, and training sessions for PD teams. PREFERRED EXPERIENCE : Hands‑on experience with physical design stages (synthesis, PnR, STA, signoff, IR / EM analysis). Strong scripting expertise : Python, Tcl, Perl, or similar. Familiarity with leading EDA tools from Synopsys, Cadence, or Siemens (ICC2 / Fusion, Innovus, PrimeTime, Tempus, RedHawk, Voltus, etc.). Experience with building and maintaining regressions, CI / CD systems, or large‑scale automation frameworks. Understanding of standard cell libraries, PDKs, and physical / timing / power model generation. Knowledge of advanced process node challenges and design constraints. ACADEMIC CREDENTIALS : Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. #LI-CC4 Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.THE ROLE : As a Silicon Design Engineer 2, you will develop, enhance, and maintain industry‑leading physical design (PD) flows, methodologies, and foundational library infrastructure. You will work closely with front‑end designers, physical design teams, CAD, and methodology leads to build scalable, automated, and robust solutions spanning all three verticals of the PD organization. Your work will directly impact execution efficiency, QoR, schedule predictability, and silicon quality across multiple programs. THE PERSON : You have a strong passion for physical design, EDA flow development, and innovative methodologies that enable efficient, high‑quality silicon. You are detail‑oriented, highly technical, and enjoy solving complex design challenges with clean, maintainable automation. You are a strong collaborator with excellent communication skills, and you thrive in an environment where you can influence methodologies and define best practices for the organization. KEY RESPONSIBILITIES : Develop, maintain, and support physical design flows across synthesis, APR, STA, power, and DRC / LVS domains. Build scalable methodologies and infrastructure for all three PD verticals (flows, libraries, execution). Own library validation infrastructure including timing, physical, and power model checking and regression. Work with EDA teams to evaluate, integrate, and qualify new tool features and methodologies. Drive automation to improve execution efficiency, debuggability, runtime, and tool QoR. Partner with physical design teams to debug flow issues, develop new features, and improve design convergence. Create regression frameworks and dashboards to ensure flow, methodology, and library quality at scale. Contribute to documentation, onboarding material, and training sessions for PD teams. PREFERRED EXPERIENCE : Hands‑on experience with physical design stages (synthesis, PnR, STA, signoff, IR / EM analysis). Strong scripting expertise : Python, Tcl, Perl, or similar. Familiarity with leading EDA tools from Synopsys, Cadence, or Siemens (ICC2 / Fusion, Innovus, PrimeTime, Tempus, RedHawk, Voltus, etc.). Experience with building and maintaining regressions, CI / CD systems, or large‑scale automation frameworks. Understanding of standard cell libraries, PDKs, and physical / timing / power model generation. Knowledge of advanced process node challenges and design constraints. ACADEMIC CREDENTIALS : Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. #LI-CC4

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.