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Junior graphic design Jobs in Magog, QC
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Junior graphic design • magog qc
- Promoted
ASIC Design Verification Engineer
XpertDirectGreater Montreal Metropolitan Area, CanadaIngénieur civil junior
PVRH-RecrutementCapitale Nationale, CA- Promoted
Lead Java Developer
Presto Recruiting SolutionsGreater Montreal Metropolitan Area, CanadaSpécialiste en design et calcul
Groupe Colas Quebec Inc - OuestCanton de Hatley, Québec, Cana, Québec, CA, J0B 2C0Spécialiste en design et calcul
ColasCanton de Hatley, Québec, Cana, Québ, CAConseiller / conseillère en design d'intérieur
Atelier Versatyl Inc.Magog, QC, CA- Promoted
Senior Software Engineer - Digital Workplace
CanonicalMartinville, QC, CanadaSenior Product Designer
Bentley SystemsHome or Hybrid, QC, CAPrototyping Design Engineer
St-AmourMonteregie- Promoted
Printed Circuit Board Design Engineer
Tundra Technical SolutionsGreater Montreal Metropolitan Area, CanadaSenior Analog Circuit Design Engineer / Architect
Ciena Canada, Inc.Bldg C, Terry Fox,Ottawa,Canada- Promoted
Lead Technique / Technical Lead
Clear DestinationGreater Montreal Metropolitan Area, CanadaPrincipal Physical Design Engineer (PNR / Physical Verification / STA / EMIR)
Cadence Design Systems, Inc.ROYAL,MOUNT- Promoted
- New!
Comptable junior
Inacre conseil inc.Sainte-Marthe, CAJunior Compensation Advisor
Treasury Board of Canada SecretariatMontréal Island, Québec- Promoted
Spécialiste en design et calcul
Colas QuébecHatley, CanadaProduct Design - Team Lead
CoveoProvince of Quebec- Promoted
Junior Frontend Engineer (React) - Montreal (Hybrid) - up to $150k + HUGE BONUS
Hunter BondGreater Montreal Metropolitan Area, Canadadesign technologist, electrical and electronics
mtls aerostructureQC, CASenior Embedded Software Test Engineer
CS GROUPQC, caASIC Design Verification Engineer
XpertDirectGreater Montreal Metropolitan Area, Canada- Full-time
We are seeking an ASIC Design Verification Engineer to join our client's innovative team. This role offers the opportunity to work on advanced verification methodologies and collaborate with global teams on cutting-edge semiconductor projects.
In this role, you will have the opportunity to develop and execute test plans, design UVM-based verification environments, and create constrained-random test cases to ensure ASIC functionality. Your responsibilities also include debugging simulation failures, tracking coverage metrics, and automating verification tasks for efficiency. Collaborating with designers, architects, and clients, you will lead verification activities, monitor progress, and drive successful project execution.
What We’re Looking For
- Experience in ASIC verification and UVM-based methodologies.
- Proficiency in SystemVerilog, Verilog, UVM, functional coverage, and formal verification.
- Strong debugging skills and experience with PCIe, Ethernet, DDR / LPDDR, AXI, ARM subsystems, etc.
- Ability to automate verification tasks and collaborate with diverse teams.