Implement state-of-art physical design power optimization methodologies into SOC project.
Maintain and enhance the power optimization methodologies in physical design flow.
Closely collaborate with SOC project design team, help / support / drive them to adopt the physical design power optimization methodology.
Preferred Experience :
Preferred 5+ years plus years of experience in physical design in digital ASIC chips.
Strong PnR, STA, IR / EM, PV knowledge / experience.
Be familiar with physical design power optimization methodologies, (eg. Clock-gating, power-gating, activity aware PnR, power friendly floor plan, DVFS, multibit re-banking de-banking, scan path power, etc.) is a plus.
Expertise in Back-End (physical design) EDA tools, especially the power calculation / optimization tools, PTPX.
Strong flow develop and custom script develop ability.
Successfully gone through several complete product development cycles.
Works well with cross-functional teams.
Good communication skills, strong interpersonal skills and the flexibility.
Preferred MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design, Bachelor's or Associate degree acceptable.