WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Understand Design-for-Test (DFT) and Design-for-Debug (DFD) architecture. Implement and deploy automated design flows to implement and verify DFT features in a complex SOC ASIC design or IP subsystem. Perform scan ATPG design rule checking, simulation and coverage analysis. Collaborate with IP teams to configure and embed DFT RTL Setup and execute design checks using both industry standard and in-house tools. Deliver Perl, Python, TCL scripts that provide scalable solutions key to DFT implementation. Create block- / chip-level Design Verification (DV) test plan. Develop test cases, behavioral functional models and testbench. Verify block- / chip-level DFT / DFD features. Monitor CAD and / or IP regression results, debug failures and analyze coverage. Skills And Experience Requirements : Experience with Perl / Python / Tcl / Shell scripting and C. Digital circuits and VLSI knowledge Experience with Verilog environment is an asset. Strong problem solving skills. Good object-oriented programming skills (C++) is a must. Good written and oral communication skills Team player with strong interpersonal skills ACADEMIC CREDENTIALS : Bachelors or Master's degree in computer engineering / Electrical Engineering Location : Markham, Ontario #LI-CS1 #-LI-Hybrid Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Understand Design-for-Test (DFT) and Design-for-Debug (DFD) architecture. Implement and deploy automated design flows to implement and verify DFT features in a complex SOC ASIC design or IP subsystem. Perform scan ATPG design rule checking, simulation and coverage analysis. Collaborate with IP teams to configure and embed DFT RTL Setup and execute design checks using both industry standard and in-house tools. Deliver Perl, Python, TCL scripts that provide scalable solutions key to DFT implementation. Create block- / chip-level Design Verification (DV) test plan. Develop test cases, behavioral functional models and testbench. Verify block- / chip-level DFT / DFD features. Monitor CAD and / or IP regression results, debug failures and analyze coverage. Skills And Experience Requirements : Experience with Perl / Python / Tcl / Shell scripting and C. Digital circuits and VLSI knowledge Experience with Verilog environment is an asset. Strong problem solving skills. Good object-oriented programming skills (C++) is a must. Good written and oral communication skills Team player with strong interpersonal skills ACADEMIC CREDENTIALS : Bachelors or Master's degree in computer engineering / Electrical Engineering Location : Markham, Ontario #LI-CS1 #-LI-HybridBenefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.