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IP Post-Silicon Validation Engineer
IP Post-Silicon Validation EngineerAMD • Markham, York Region, CA
IP Post-Silicon Validation Engineer

IP Post-Silicon Validation Engineer

AMD • Markham, York Region, CA
26 days ago
Job type
  • Full-time
Job description

Join to apply for the IP Post-Silicon Validation Engineer role at AMD .

This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$150,400.00 / yr - $225,600.00 / yr

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The AMD NBIO Team is on the lookout for a dynamic, upbeat IP Validation Design Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person

  • Must have excellent written and verbal communication skills.
  • Must excel in a dynamic team working environment.
  • Leadership and mentoring skills a definite asset.
  • Must be a self-starter and be able to independently drive tasks to completion.

Key Responsibilities

  • Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s.
  • Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts / automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
  • Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs.
  • Engaging on pre-silicon ‘shift left’ activities with cross-functional teams including but not limited to Design Verification (DV), Diagnostics, Emulation and other software / hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
  • Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.
  • Developing knowledge of system architecture / debug and other internal IP’s. Supporting issues on customer platforms as requested by customer support teams.
  • Preferred Experience

  • Experience in digital logic design / verification / post-silicon validation.
  • Extensive experience with ASIC debug techniques and methodologies.
  • Extensive knowledge of physical and protocol levels of common high-speed interfaces an asset.
  • Extensive experience with board / platform-level debug, including clock / power delivery, sequencing, analysis, and optimization.
  • Strong scripting skills (eg. Ruby, Python).
  • Extensive experience with common lab equipment, including protocol / logic analyzers, oscilloscopes, etc.
  • In-depth knowledge of PC architectures / PCIe protocol is an asset.
  • Must have excellent written and verbal communication skills.
  • Must excel in a dynamic team working environment.
  • Leadership and mentoring skills a definite asset.
  • Must be a self-starter and be able to independently drive tasks to completion.
  • Academic Credentials

  • Bachelor’s or master’s degree majoring in EE, CS or related field.
  • Location

    Markham, Vancouver

    Benefits offered are described : AMD benefits at a glance.

    AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

    Seniority level

    Mid-Senior level

    Employment type

    Full-time

    Job function

    Engineering and Information Technology

    Industries

    Semiconductor Manufacturing

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    Validation Engineer • Markham, York Region, CA

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