Senior Memory Subsystem Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world.

Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded.

Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges.

We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance THE ROLE : The Memory IO team is looking for passionate and experienced Verification engineers for the verification of high-speed LPDDRx, DDRx and associated IPs through the utilization of complex co-simulation hybrid environments and traditional UVM methodologies.

Be a part of the definition, design, and development phase of industry-leading Memory IP, as well as the overall memory subsystem.

This opportunity includes verification of the memory subsystem across multiple product lines as well as verification of pre-silicon production level firmware verification.

THE PERSON : Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a new team to develop an end to end verification solution from IP / subsystem verification through advanced technics, including BIOS verification.

Are you looking for a ground floor opportunity that requires being a self-starter and the ability to independently drive tasks to completion?

We are also looking for strong interpersonal and communication skills this position will be working collaboratively across the AMD organization! If this sounds like you, please apply! KEY RESPONSIBILITIES : Excellent knowledge of C, C++, SystemVerilog, UVM object-oriented design as well as scripting language.

Experience in ground up development and verification using UVM / SystemVerilog with IP and Subsystem verification as main objective using VCS.

Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification.

In depth knowledge of code and functional coverage constructs as well as test plan to coverage relationships. Development and debug of co-verification environment with production level firmware.

Development and maintenance of test suite through firmware feature set modification as well as custom transactor-based stimulus development.

Subsystem and block level test plan development in relationship to FW / HW co-verification and maintenance as well as subsystem test plan development.

Ability to adapt and learn new toolsets and framework, making updates as needed. PREFERRED EXPERIENCE : Experience in hardware / Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench.

Knowledge and development of monitors and checkers and / or experience developing SVA / OVL and synthesizable assertions.

Experience with DDR / JEDEC standard IP, DDR PHY, or Memory Controller verification. Understanding and experience utilizing architectural models.

Knowledge of SystemC and Python. Zebu Emulation verification and debug experience. Memory VIP integration, initialization, and debug experience.

End to end verification experience from front end verification through lab bring up Strong understanding of synchronization techniques (handshakes, message passing);

knowledge of hardware level clocking and multi-domain simulation synchronization. Strong knowledge of git and perforce. Development and maintenance of regressions as well as coverage databases.

SoC IP knowledge and architectural understanding of the purpose of each IP. ACADEMIC CREDENTIALS : Bachelor's degree in Electrical or Computer Engineering and relevant experience, or Master's or PhD degree in Electrical or Computer Engineering with relevant experience.

LOCATION : Raleigh, NC Bellevue, WA, Boxborough, MA, Santa Clara, CA, Austin, TX #LI-SH1 #HYBRID Benefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE : The Memory IO team is looking for passionate and experienced Verification engineers for the verification of high-speed LPDDRx, DDRx and associated IPs through the utilization of complex co-simulation hybrid environments and traditional UVM methodologies.

Be a part of the definition, design, and development phase of industry-leading Memory IP, as well as the overall memory subsystem.

This opportunity includes verification of the memory subsystem across multiple product lines as well as verification of pre-silicon production level firmware verification.

THE PERSON : Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a new team to develop an end to end verification solution from IP / subsystem verification through advanced technics, including BIOS verification.

Are you looking for a ground floor opportunity that requires being a self-starter and the ability to independently drive tasks to completion?

We are also looking for strong interpersonal and communication skills this position will be working collaboratively across the AMD organization! If this sounds like you, please apply! KEY RESPONSIBILITIES : Excellent knowledge of C, C++, SystemVerilog, UVM object-oriented design as well as scripting language.

Experience in ground up development and verification using UVM / SystemVerilog with IP and Subsystem verification as main objective using VCS.

Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification.

In depth knowledge of code and functional coverage constructs as well as test plan to coverage relationships. Development and debug of co-verification environment with production level firmware.

Development and maintenance of test suite through firmware feature set modification as well as custom transactor-based stimulus development.

Subsystem and block level test plan development in relationship to FW / HW co-verification and maintenance as well as subsystem test plan development.

Ability to adapt and learn new toolsets and framework, making updates as needed. PREFERRED EXPERIENCE : Experience in hardware / Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench.

Knowledge and development of monitors and checkers and / or experience developing SVA / OVL and synthesizable assertions.

Experience with DDR / JEDEC standard IP, DDR PHY, or Memory Controller verification. Understanding and experience utilizing architectural models.

Knowledge of SystemC and Python. Zebu Emulation verification and debug experience. Memory VIP integration, initialization, and debug experience.

End to end verification experience from front end verification through lab bring up Strong understanding of synchronization techniques (handshakes, message passing);

knowledge of hardware level clocking and multi-domain simulation synchronization. Strong knowledge of git and perforce. Development and maintenance of regressions as well as coverage databases.

SoC IP knowledge and architectural understanding of the purpose of each IP. ACADEMIC CREDENTIALS : Bachelor's degree in Electrical or Computer Engineering and relevant experience, or Master's or PhD degree in Electrical or Computer Engineering with relevant experience.

LOCATION : Raleigh, NC Bellevue, WA, Boxborough, MA, Santa Clara, CA, Austin, TX #LI-SH1 #HYBRIDBenefits offered are described : AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.