ASIC Digital Design, Staff Engineer

Synopsys is at the heart of all the advanced silicon design, supplying the essential tools and intellectual properties to enable semiconductor design, verification, and production. We’re powering the state-of-the-art design market with the world’s most advanced technologies for chip design and software security.

DDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of DDR PHY IP products. All current and next-generation technologies are being developed by the DDR PHY IP team, where both digital and analog components complement each other in creating high-performance, high-bandwidth, low-latency, and low-power products.

We are looking for a Staff ASIC Digital Design Engineer to join Synopsys' DDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare DDR PHY IP solution. Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solutions; your passion and expertise will shape the next generation of product innovation, performance, and efficiency.

Job Description

• Contribute to all phases of designs of DDR PHY IP from design specification to productization, including a certain level of customer support into their SoCs.
• Design and micro-architect DDR PHY IP writing Verilog and SystemVerilog code and design specifications.
• Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members.
• Analyze and fix Lint, CDC / RDC, DFT, Timing, and power issues.
• Maintain and improve design automation flow and process.

Required Skills

J-18808-Ljbffr