PDK Enablement Engineering Specialist

Cadence is recruiting a PDK Enablement Engineering Specialist.

Job Summary

As a PDK Enablement Engineering Specialist, you will provide and support the tools and foundry files that enable circuit implementation teams building chips used in cars, cell phones, data centers, and more, using the latest fabrication technologies such as FinFET and Gate All‑Around. You will work closely with analytic and layout engineers and will be responsible for enabling foundry PDKs for Cadence’s analog design and custom layout teams.

Responsibilities

• Download, format, install, QA‑test, release, and maintain foundry PDK data for the design teams.
• Analyze initial PDKs and subsequent versions to understand the impact of design libraries, device models, DRC, LVS, extraction rules, and reliability requirements on circuit design.
• Share findings and best‑practice knowledge with the design teams.
• Create and maintain automation and regression routines to simplify installation and ensure collateral works across multiple tool versions.
• Customize foundry data to improve design efficiency and quality.
• Collaborate with foundries on PDK development, discussing novelties, bugs, and issues.
• Work with Cadence R&D teams to leverage PDK learnings for tool development.

Qualifications

Salary & Benefits

The annual salary range for British Columbia is 89,600 CAD to 166,400 CAD. You may also be eligible for incentive compensation including bonus, equity, and benefits. Our benefits program includes paid vacation, paid holidays, a 401(k) plan with employer match, an employee stock purchase plan, and various medical, dental, and vision plan options.

EEO Statement

We welcome applications from candidates with disabilities and from equity‑seeking groups. If you have accessibility needs during the application or interview process, please let us know.

Job Details

Job Description (English)

Cadence Design Systems is seeking PDK enablement engineering specialists to enable foundry PDKs and support the growing analog design and custom layout team building IP using the Cadence design tools such as Virtuoso, Pegasus, and Quantus. The role focuses on ensuring that the latest technology nodes from leading‑edge foundries—gate all‑around, finfet, 2D & 2.5D packaging, and 3D IC stacking—are available and reliable for our design teams.

Job Description (French)

Cadence Design Systems recherche des ingénieurs spécialisés dans les PDK pour bâtir et supporter les fichiers et outils nécessaires à la conception de circuits intégrés dans les fonderies les plus avancées. Ces fichiers seront utilisés par les équipes de conception et de layout analogique. L’équipe développe des circuits (IP) à l’aide des logiciels Cadence (Virtuoso, Pegasus, Quantus, etc.) afin de créer des interfaces à haut débit utilisées dans les puces présentes dans les automobiles, les téléphones portables, les centres de données, etc.

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