Principal Design Verification Engineer
We Are :
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are :
A highly skilled and experienced ASIC Design Verification Engineer who thrives in a dynamic and innovative environment. With a strong background in ASIC verification at both the SOC and block levels, you possess exceptional skills in Verilog, System Verilog, and scripting languages like Perl / Python. Your proficiency in UVM verification environments and industry tools allows you to optimize verification processes efficiently. You have a knack for debugging and can independently root cause issues, providing technical leadership from initial specification to tape out. Your excellent communication and problem-solving skills enable you to work seamlessly with architects and RTL designers. Experience in DDR PHY and memory subsystems is a plus.
What You’ll Be Doing :
The Impact You Will Have :
What You’ll Need :
Who You Are :
The Team You’ll Be A Part Of :
You will join our dedicated DDR PHY IP team, a group of experts focused on delivering high-quality integrated IP subsystems. Our team works collaboratively across various functions to ensure the successful design and verification of advanced silicon chips. We are committed to driving innovation and excellence in all our projects.
Rewards and Benefits :
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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