Staff PLL Analog Design Engineer

Shape PLL and timing circuitry at SiTime, combining phase-noise knowledge, transistor analysis, and hands-on prototype characterization for advanced products. This Staff Analog Design Engineer develops analog circuits and key blocks for high-performance timing products. The work requires understanding transistor behavior, circuit noise theory, phase-noise concepts, and top-level architecture. You will support silicon development, product validation, qualification, release, and customer applications through cross-functional collaboration. Key Responsibilities:

Design PLLs and supporting analog timing circuits Incorporate circuit blocks into complete chip designs Test and debug laboratory prototypes Characterize prototypes and support product validation Support qualification and new product release Requirements:

Master’s or PhD degree in Electrical Engineering Six or more years of relevant analog or mixed-signal IC design Knowledge of device physics and advanced process technologies Understanding of transistor behavior, noise, and phase noise Hands-on laboratory testing and characterization experience Apply PLL, phase-noise, and analog circuit expertise to SiTime’s MEMS-based precision timing technology development.

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