Formal Verification Engineer

The Role

The Formal Verification team is dedicated to formal verification. It provides formal functional and security verification for a broad range of IPs including input-output virtualization, PCIe Root-Complex/End-Point, inter-chiplet highspeed connections, etc. We are currently looking for formal verification engineers with expertise in IP verification, formal verification methodologies, highspeed IO bus protocols and team leadership to take on the challenges. In these highly visible roles, the qualified candidates will use cutting edge formal verification technologies to verify the newest IPs resulting in a level of design quality not paralleled by classical verification.

Key Responsibilities

• Collaborating with architects and designers to understand the design intents
• Creating and executing formal verification plans for design blocks
• Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution
• Optimizing runtime using formal techniques
• Collecting and reporting status and progress
• Improving formal setups based on feedbacks from reviews, metrics, etc.
• Leading and coordinating verification activities for a small team
• Training and coaching junior engineers
• Developing working procedures, flows and infra
• Handling complicated formal problems

Preferred Experience

• Combined ASIC/FPGA design and verification experience.
• Verify complex IPs including I/O virtualization, PCIe Root Complex/End Point, and high-speed inter-chiplet interconnects using advanced formal verification methodologies.
• Develop and execute formal functional and security verification strategies to ensure industry-leading design quality and coverage.
• Apply expertise in high-speed I/O protocols, IP verification, and formal verification technologies to validate next-generation semiconductor designs.
• Drive adoption of cutting-edge formal verification and automation techniques to improve verification efficiency and accelerate closure.
• Provide technical leadership, mentorship, and methodology guidance across formal verification projects and teams.
• Demonstrate strong hands‑on experience with AI-based formal verification, including AI‑assisted property generation, proof optimization, coverage analysis, root‑cause debugging, and verification closure.
• Collaborate closely with architecture, RTL design, DV, and silicon teams from concept through tapeout and post‑silicon validation.
• Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods.
• Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign‑off and commercial formal tools (VC‑Formal, JasperGold, Questa Formal, etc.).
• Extensive experience verifying complex, packet or control based designs.
• Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB, AXI, etc.
• Experience with verification of Hardware‑Firmware interaction is highly desirable.

Academic Credentials

• BS (or higher) degree in Electronics/Electrical or Computer Engineering desired

Location

• Markham, Vancouver, Ottawa, Calgary

Benefits

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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