Technical Staff Engineer - Emulation

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

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Job Description:

The Architecture Co-Verification team (ACOV) is an exciting, fast-paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry-leading HW emulators (such as Cadence Palladium and Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations.

As an Emulation Engineer, you will be working closely with architects, hardware designers, firmware engineers, and verification teams throughout the SoC development process.

This is a role for a versatile engineer that enjoys the challenges of HW/FW co-development and system-level co-verification using leading-edge HW emulators and FPGA platforms.It’sa high-visibility role that will develop a wide range of skills and exceptional problem-solving abilities.

Responsibilities could include but are not limited to the following:

• Managing amulti-location, cross functional team of engineers and technicians

• Planning and developing a common test ecosystem across pre/post silicon

• Using Jira to plan and track project tasks and report results

• Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing emulation test plans.

• Utilizationof test and defect tracking tools to document and report on verification progress and product quality

• Effectively present technical information to small teams of engineers.

Requirements/Qualifications:

• BS/MS/PhD in degree or higher in Electrical/Electronic Engineering or Computer Engineering

• 12.5+ years of experience in leading FPGA/ASIC/EDA development,simulationand verification projects.

• 2+ years' experience with one or more serial storage protocols such as SAS, SATA,NVMe, CXL and thorough knowledge of the PCIe interface.

• In-depth knowledge of CXL protocols.

• Experience working with large scale FPGA solutions

• Thorough understanding of digital design, RTLcodingand simulation

• Prior knowledge and experience in HDL languages (Verilog, VHDL andSystemVerilog)

• Working knowledge of C/C++,TCLor Perl/Python languages.

• Excellent verbal and writtencommunicationalskills.

• Effective team player, collaborator, and a great motivator forteam.

• Ability to work in a multi-location, cross functional team

• Proficiencyin lab equipment usage for test and debug

• Microcontroller programming skills are desirable

Desirable:

• Cadence infrastructure support and maintenance flows

• Proficient in using Agile methodologies and Bug tracking tools

Optional Desired Skills that can be included/replaced above-

• Experience with RAID HBA’s, SAS Controllers and their associated Software Testing Strategies.

• Experience with Computer System I/O hierarchies and interconnects, specifically with PCI-Express protocols and infrastructure.

• Experience with Storage IO Generators (IOMeter, Medusa, FIO).

• Knowledgeable inuseof tool chains and debug tools.

• Experience with test automation, testing methodologies, and test tools.

• Isolation and resolution of complex software & firmware problems in embedded real-time systems.

• Familiarity with hardware design and implementation.

• Experience troubleshooting server system hardware and networking infrastructure to root cause issues.

• Troubleshoot and resolve complex problems in embedded multi-core real-time systems.

• Knowledge of Embedded Linux development as well as RTOS constructs including processes, threads, scheduling, synchronization mechanisms, memorymanagement.

• Knowledge of MIPS, ARM, or RISC-V CPUarchitecture and firmware programming

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:The annual base salary range for this position is $86,000-$186,000.*

*Range is dependent on numerous factors including job location, skills and experience.

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