Partner with ML and Software teams as a key hardware domain expert, translating complex silicon constraints into actionable insights for model training and agentic design
Develop high-quality RTL libraries, IP blocks and processor designs that serve as training data and composable parts of our environment
Build and maintain an ecosystem of benchmarks and reference designs used to evaluate and increase the design velocity of our tools
Execute and refine novel chip design methodologies, from architectural specs to synthesized netlists to complete bitstreams to identify where AI can optimize the flow
Generate and curate massive datasets of syntactic and semantic hardware code to improve model robustness
Implement robust verification environments, writing the SystemVerilog/UVM testbenches and assertions with our tools that ensure our generated designs are correct-by-construction
What you must have:
Bachelor’s or Masters in Computer Science, Electrical Engineering, or a closely related field
5-10 years of experience in RTL design, or a combination of design and verification
Experience with AMD/Xilinx (Vivado, Vitis) and Altera/Intel (Quartus) ecosystems or ASIC physical design chains, including SoC and IP integrations
Experience with hands-on debugging - simulators, waveform viewing, coverage collection
Salary/Rate Range: $200.00 -$300.00
Thank you for your interest in this opportunity. If you are selected to move forward in the process, we will contact you directly. If you do not hear from us, we encourage you to continue visiting our website for other roles that may be a good fit.
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