Design Engineer

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality. The candidate will primarily be responsible for the verification of digital RTL and development of reusable verification components and environments. It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure. The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status. The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills. The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies. The candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).

Design IP is growing organization within Cadence and our complete IP portfolio can be found here http : / / ip.cadence.com / ipportfolio / ip-portfolio-overview.

Responsibilities

• Verify digital RTL and develop reusable verification components and environments.
• Contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.
• Communicate project development progress and status with technical staff across teams and geographies.
• Collaborate with design, verification, project management, and analog / digital design teams as needed.
• Work as part of a small, focused team and manage tasks to meet project timelines.

Qualifications

Preferred Experience

Location & Travel

Montreal, Quebec, Canada office. Travel required by job function (expectation is 5% travel or less).

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering and Research

Industries

Semiconductor Manufacturing and Manufacturing

Cadence is an equal-opportunity employer committed to hiring a diverse workforce.

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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

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