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Staff ASIC Verification Engineer

Staff ASIC Verification Engineer

InfineraOttawa, Canada
Il y a plus de 30 jours
Salaire
65 CAD–80 CAD par heure
Type de contrat
  • Temps plein
Description de poste

Responsibilities

  • Contribute significantly to verification infrastructure development
  • Development of System Verilog / UVM-based protocol / traffic generators / checkers, development of test plan based on functional requirements as well as applicable standards requirements.

Requirements

  • Masters degree desired, Bachelor's degree in CS / EE is required.
  • 8+ years of relevant experience in the ASIC verification field.
  • Should have worked on developing / implementing test plans at the block or sub-chip levels for complex ASICs.
  • Fluent in System Verilog and scripting languages such as Python
  • Must have intimate knowledge of UVM methodology.
  • Knowledgeable about assertions and functional coverage
  • Experience with code coverage and formal verification tools; familiarity with evolving verification methodologies.
  • Very good communication skills and ability and desire to work in a geographically diverse team environment.
  • Will be responsible for the definition, development, and execution of self-checking tests for complex digital ASICs.
  • Knowledge of DSP and / or FEC will be desirable
  • LI-SR2