Design Verification Engineer - GPU

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

As a Design Verification Engineer, you will work with leading industry tools and methodologies to contribute to the verification of Cache & Memory Management IPs which are a part of the Graphics Core IP (GFXIP). You will work closely with architects, other design engineers and the verification team to delivery highest quality verification on schedule. Furthermore, you will also collaborate with the Power Attainment teams to reach performance and power targets. Finally, you may also be required to support post-silicon bring-up, diagnostics and validation teams.

THE PERSON:

The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design or micro-architecture issue. You should be able to strike a balance between collaborative problem-solving and independent solution development.

KEY RESPONSIBILITIES:

• Colloborate closely with the architect, RTL designers and other verification engineers to achieve verification closure within project schedules;
• Create, reuse and debug testbenches, verification components and tests for verification of the design;
• Be responsible for functional, power and performance verification of a block, including verification planning, execution and DV closure;
• Develop and execute test and coverage plans to ensure the functional, performance and power completeness;
• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.

PREFERRED EXPERIENCE:

• Strong Verification experience on large ASIC development projects;
• Solid understanding of Computer Architecture and Digital Design concepts;
• Very strong background in Verilog, System Verilog, C/C++/OOO coding techniques.
• Experience working with UVM, OVM or equivalent.
• Experience with constrained random verification, functional coverage and assertions.
• Experience with formal verification is an added advantage.
• Familiarity with scripting languages: Perl/TCL/Ruby/Bash/python.
• Experience working with industry standards tools such Synopsys VCS, VC Formal, DVE, Verdi, GDB or equivalent.
• Strong analytical skills and attention to detail.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering

#LI-CJ3

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

As a Design Verification Engineer, you will work with leading industry tools and methodologies to contribute to the verification of Cache & Memory Management IPs which are a part of the Graphics Core IP (GFXIP). You will work closely with architects, other design engineers and the verification team to delivery highest quality verification on schedule. Furthermore, you will also collaborate with the Power Attainment teams to reach performance and power targets. Finally, you may also be required to support post-silicon bring-up, diagnostics and validation teams.

THE PERSON:

The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design or micro-architecture issue. You should be able to strike a balance between collaborative problem-solving and independent solution development.

KEY RESPONSIBILITIES:

• Colloborate closely with the architect, RTL designers and other verification engineers to achieve verification closure within project schedules;
• Create, reuse and debug testbenches, verification components and tests for verification of the design;
• Be responsible for functional, power and performance verification of a block, including verification planning, execution and DV closure;
• Develop and execute test and coverage plans to ensure the functional, performance and power completeness;
• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.

PREFERRED EXPERIENCE:

• Strong Verification experience on large ASIC development projects;
• Solid understanding of Computer Architecture and Digital Design concepts;
• Very strong background in Verilog, System Verilog, C/C++/OOO coding techniques.
• Experience working with UVM, OVM or equivalent.
• Experience with constrained random verification, functional coverage and assertions.
• Experience with formal verification is an added advantage.
• Familiarity with scripting languages: Perl/TCL/Ruby/Bash/python.
• Experience working with industry standards tools such Synopsys VCS, VC Formal, DVE, Verdi, GDB or equivalent.
• Strong analytical skills and attention to detail.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering

#LI-CJ3

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.