Physical Design Engineer (DSP)

Company : Qualcomm Canada ULC

Job Area : Engineering Group, Engineering Group >

ASICS Engineering

General Summary

QCT’s DSP Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical Design Engineer, you will innovate, develop, and implement DSP cores using state‑of‑the‑art tools and technologies. This role requires strong expertise in physical design flow, tapeout readiness, and Power, Performance, and Area (PPA) optimization for advanced technology nodes.

Key Responsibilities

• Own and execute complete Physical Design flow from netlist to GDSII, including :
• Floorplanning, power planning, IR‑drop analysis
• Placement, MMMC clock tree synthesis, routing
• Timing optimization and closure across multiple modes and corners
• Perform PPA analysis and optimization to meet aggressive power, performance, and area targets.
• Develop and enable low‑power implementation methods and customized P&R strategies for area reduction and performance improvement.
• Debug timing violations, implement timing fixes, and roll in functional ECOs.
• Conduct RC extraction, signal integrity, crosstalk noise / delay analysis, and formal verification.
• Manage tapeout activities, ensuring sign‑off for DRC, LVS, timing, power integrity, and reliability.
• Collaborate with RTL, architecture, and verification teams to influence design decisions for optimal PPA.
• Contribute to flow enhancements and automation using scripting (Perl / TCL, Python, Linux shell).

Required Qualifications

Hands‑on expertise with :

Preferred Skills

Why Join Us?

Minimum Qualifications

Applicants

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