SOC / IP Power Management Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE : A senior SOC Power Management design engineer who designs, develops, and implements techniques like low-power modes and clock gating to optimize energy efficiency in a single integrated circuit. Expertise in power architecture solutions, specializing in areas like microprocessors, GPUs, and machine learning accelerators to optimize power efficiency and performance. This involves creating power management algorithms, developing power models, and collaborating with cross-functional teams to implement and validate power-saving features throughout the design cycle THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES : Gather requirements, prototype, and develop SoC and IP-level power management architecture, including power and thermal management solutions. Design and execute experiments on silicon to guide power optimizations and prototype power management features Partner with SoC, IP, system, and software teams to align power management plans and ensure cohesive support across the development lifecycle. Lead and drive the bring-up and development of power management features from initial design and verification to the final product release. Analysis and modeling : Create power models and scripts for analysis of performance / power trade-offs. Methodology Development : Research, develop, and deploy methodologies and automated flows to enhance power analysis and modeling efficiency. Collaboration : Work with other teams, including RTL, Architecture, Physical Design, Emulation, Software, Firmware to ensure power requirements are met across the hardware-software stack. PREFERRED EXPERIENCE : Extensive industry experience, with a specialization in low-power-processor architectures and / or power management technologies. Hands-on experience running power / performance optimization experiments in the lab. Experience developing embedded power management firmware. In-depth understanding of power-saving methods such as clock-gating, power-gating, and DVFS. Solid grasp of processor architecture and workload characteristics Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design). Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and power simulation / analysis tools (e.g., PowerArtist, PTPX) Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges. ACADEMIC CREDENTIALS : Master's degree or PhD in a relevant field, such as Electrical or Computer Engineering LOCATION : Markham, Vancouver, Ottawa #LI-SC3 Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.THE ROLE : A senior SOC Power Management design engineer who designs, develops, and implements techniques like low-power modes and clock gating to optimize energy efficiency in a single integrated circuit. Expertise in power architecture solutions, specializing in areas like microprocessors, GPUs, and machine learning accelerators to optimize power efficiency and performance. This involves creating power management algorithms, developing power models, and collaborating with cross-functional teams to implement and validate power-saving features throughout the design cycle THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES : Gather requirements, prototype, and develop SoC and IP-level power management architecture, including power and thermal management solutions. Design and execute experiments on silicon to guide power optimizations and prototype power management features Partner with SoC, IP, system, and software teams to align power management plans and ensure cohesive support across the development lifecycle. Lead and drive the bring-up and development of power management features from initial design and verification to the final product release. Analysis and modeling : Create power models and scripts for analysis of performance / power trade-offs. Methodology Development : Research, develop, and deploy methodologies and automated flows to enhance power analysis and modeling efficiency. Collaboration : Work with other teams, including RTL, Architecture, Physical Design, Emulation, Software, Firmware to ensure power requirements are met across the hardware-software stack. PREFERRED EXPERIENCE : Extensive industry experience, with a specialization in low-power-processor architectures and / or power management technologies. Hands-on experience running power / performance optimization experiments in the lab. Experience developing embedded power management firmware. In-depth understanding of power-saving methods such as clock-gating, power-gating, and DVFS. Solid grasp of processor architecture and workload characteristics Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design). Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and power simulation / analysis tools (e.g., PowerArtist, PTPX) Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges. ACADEMIC CREDENTIALS : Master's degree or PhD in a relevant field, such as Electrical or Computer Engineering LOCATION : Markham, Vancouver, Ottawa #LI-SC3

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.